ADP1828LC-EVALZ Analog Devices Inc, ADP1828LC-EVALZ Datasheet - Page 22

• Manufacturer Part Number: ADP1828LC-EVALZ
• Description: BOARD EVALUATION ADP1828LC
• Manufacturer: Analog Devices Inc

Specifications of ADP1828LC-EVALZ

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.8V
• Current - Output: 5A
• Voltage - Input: 5.5 ~ 13.2V
• Regulator Topology: Buck
• Frequency - Switching: 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ADP1828
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

ADP1828
Depending on component selection, one zero might already be
generated by the ESR of the output capacitor. Calculate this zero
corner frequency, f
Figure 37 shows a typical Bode plot of the LC filter by itself.
The gain of the LC filter at crossover can be linearly
approximated from Figure 37 as
If f
difference between the exact solution and the linear approxi-
mation in Equation 19.
To compensate the control loop, the gain of the system must
be brought back up so that it is 0 dB at the desired crossover
frequency. Some gain is provided by the PWM modulation itself.
For systems using the internal oscillator, this becomes
PHASE
GAIN
ESR
A
A
A
A
f
≈ f
ESR
FILTER
FILTER
MOD
MOD
0dB
0°
–90°
–180°
CO
=
, then add another 3 dB to account for the local
=
2
=
=
π
=
–40dB/dec
20
20
−
R
A
40
log
ESR
LC
log
1
dB
ESR
f
C
LC
⎛
⎜
⎜
⎝
+
Figure 37. LC Filter Bode Plot
⎛
⎜
⎜
⎝
OUT
1
, as
–20dB/dec
V
V
A
0 .
×
V
RAMP
IN
ESR
log
V
IN
f
ESR
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
f
f
ESR
LC
f
CO
⎞
⎟
⎟
⎠
Φ
A
FILTER
−
FILTER
20
dB
×
log
f
SW
⎛
⎜
⎜
⎝
f
f
ESR
CO
FREQUENCY
⎞
⎟
⎟
⎠
(18)
(19)
(20)
(21)
Rev. C | Page 22 of 36
Note that if the converter is being synchronized, the ramp
voltage, V
frequency increase over the nominal setting of the FREQ pin:
For example, if FREQ is grounded or connected to VREG, then
f
by a resistor, then f
by the resistor. V
f
over. The total gain of the system, therefore, is given by
where:
A
A
the ESR zero.
A
Additionally, the phase of the system must be brought back
up to guarantee stability. Note from the Bode plot of the filter
that the LC contributes −180° of phase shift (see Figure 37).
Because the error amplifier is an integrator at low frequency,
it contributes an initial −90°. Therefore, before adding com-
pensation or accounting for the ESR zero, the system is already
down −270°. To avoid loop inversion at crossover, or −180°
phase shift, a good initial practical design is to require a phase
margin of 60°, which is therefore an overall phase loss of −120°
from the initial low frequency dc phase. The goal of the com-
pensation is to boost the phase back up from −270° to −120°
at crossover.
Two common compensation schemes are used, which are
sometimes referred to as Type II or Type III compensation,
depending on whether the compensation design includes
two or three poles (see the Type II Compensator and Type III
Compensator sections). Dominant-pole compensation, or
single-pole compensation, is referred to as Type I compensation,
but it is not very useful for dealing successfully with switching
regulators.
If the zero produced by the ESR of the output capacitor provides
sufficient phase boost at crossover, Type II compensation is
adequate. If the phase boost produced by the ESR of the output
capacitor is not sufficient, another zero is added to the compen-
sation network, and thus Type III is used.
In Figure 38, the location of the ESR zero corner frequency
gives a significantly different net phase at the crossover
frequency.
FREQ
FREQ
MOD
FILTER
COMP
. The rest of the system gain needs to reach 0 dB at cross-
A
V
is 300 kHz or 600 kHz, respectively. If the frequency is set
is the gain of the PWM modulator.
is the gain of the compensated error amplifier.
RAMP
T
is the gain of the LC filter including the effects of
= A
RAMP
=
MOD
1
, is lower than 1.0 V by the percentage of
0 .
+ A
V
RAMP
FREQ
⎛
⎜ ⎜
⎝
FILTER
f
f
is greater than 1.0 V if f
FREQ
SYNC
is 300 kHz and f
+ A
⎞
⎟ ⎟
⎠
COMP
SYNC
is the frequency set
SYNC
is less than
(22)
(23)