ADP1828LC-EVALZ Analog Devices Inc, ADP1828LC-EVALZ Datasheet - Page 8

• Manufacturer Part Number: ADP1828LC-EVALZ
• Description: BOARD EVALUATION ADP1828LC
• Manufacturer: Analog Devices Inc

Specifications of ADP1828LC-EVALZ

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.8V
• Current - Output: 5A
• Voltage - Input: 5.5 ~ 13.2V
• Regulator Topology: Buck
• Frequency - Switching: 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ADP1828
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

ADP1828
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
QSOP
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
LSCSP
Pin No.
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 3. 20-Lead QSOP Pin Configuration
COMP
FREQ
SYNC
VREG
GND
TRK
EN
FB
SS
IN
10
Mnemonic
FREQ
SYNC
EN
IN
VREG
GND
COMP
FB
TRK
SS
PGOOD
PV
DL
PGND
CSL
SW
DH
BST
1
2
3
4
5
6
7
8
9
(Not to Scale)
ADP1828
TOP VIEW
Description
Frequency Control Input. Low for 300 kHz, high for 600 kHz, or connect a resistor from FREQ to GND to
set the free-running frequency between 300 kHz and 600 kHz.
Frequency Synchronization Input. Accepts external signals between 300 kHz and 600 kHz if FREQ is set
to low, or between 600 kHz and 1.2 MHz if FREQ is set to high. If f
synchronization frequency range is from f
or VREG. V
Enable Input. Drive EN high or tristate EN to turn on the ADP1828 controller, and drive it low to turn off.
Connect EN to IN for automatic startup.
Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 20 V to power the ADP1828 from
LDO, VREG; tie PV to VREG. For input voltages between 3 V and 5.5 V, tie IN, PV, and VREG together.
Output of the Internal Linear Regulator (LDO). The internal circuitry and gate drivers are powered from
VREG. Bypass VREG to AGND plane with 1 μF ceramic capacitor for stable operation, for example, a 10 V
X5R 1 μF ceramic capacitor is sufficient. The VREG output is 5 V when IN = 5 V + dropout. Connect IN to
VREG and PV when IN = 3 V to 5.5 V. For applications with IN < 5.5 V and IN not connected to VREG, keep
in mind that VREG = VIN – dropout. VREG needs to be ≥3 V for proper operation.
Ground for Internal Circuits. Tie the bottom of the feedback dividers to this GND.
Error Amplifier Output. Connect an RC network from COMP to FB for loop compensation.
Voltage Feedback. Connect a resistor divider from the buck regulator output to GND and tie the tap to
FB to set the output voltage.
Tracking Input. To track a master voltage, drive TRK from a voltage divider from the master voltage. If
the tracking function is not used, connect TRK to VREG.
Soft Start Control Input. Connect a capacitor from SS to GND to set the soft start period.
Open-Drain Power-Good Output. Sinks current when FB is out of regulation. Connect a pull-up resistor
from PGOOD to VREG.
Positive Input Voltage for Gate Driver DL. When IN is 3 V to 5.5 V, connect IN to VREG and PV. Connect a
1 μF bypass capacitor from PV to PGND. When IN = 5.5 V to 20 V, connect PV to VREG.
Low-Side (Synchronous Rectifier) Gate Driver Output.
Power GND. Ground for gate driver.
Current Sense Comparator Inverting Input. Connect a resistor between CSL and SW to set the current-
limit offset.
Switch Node Connection.
High-Side (Switch) Gate Driver Output.
Boost Capacitor Input. Powers the high-side gate driver DH. Connect a 0.22 μF to 0.47 μF ceramic
capacitor from BST to SW and a Schottky diode from PV to BST.
20
19
18
17
16
15
14
13
12
11
CLKOUT
CLKSET
BST
DH
SW
CSL
PGND
DL
PV
PGOOD
SYNC
can be driven up to 6 V even when V
Rev. C | Page 8 of 36
OSC
up to 600 kHz. If SYNC is not used, connect SYNC to GND
(Not to Scale)
NOTES
1. CONNECT THE BOTTOM EXPOSED PAD OF THE
IN
COMP
VREG
LFCSP PACKAGE TO SYSTEM AGND PLANE.
is less than 6 V.
GND
Figure 4. 20-Lead LFCSP Pin Configuration
EN
IN
1
2
3
4
5
ADP1828
OSC
VIEW
TOP
is set by R
12
15 DH
14
13
11 DL
FREQ
SW
CSL
PGND
, then the