ISL8105BEVAL1Z Intersil, ISL8105BEVAL1Z Datasheet - Page 11

• Manufacturer Part Number: ISL8105BEVAL1Z
• Description: EVAL BOARD ISL8105B
• Manufacturer: Intersil

Specifications of ISL8105BEVAL1Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.8V
• Current - Output: 15A
• Voltage - Input: 9.6 ~ 14.4V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL8105B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

earlier. Locate the capacitor, C
the BOOT and LX pins. All components used for feedback
compensation (not shown) should be located as close to the
IC as practical.
Feedback Compensation
This section highlights the design considerations for a
voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 9).
Figure 9 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable to the
ISL805B circuit. The output voltage (V
the reference voltage, V
(COMP pin voltage) is compared with the oscillator (OSC)
triangle wave to provide a pulse-width modulated wave with
an amplitude of V
smoothed by the output filter (L and C). The output filter
capacitor bank’s equivalent series resistance is represented
by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V
gain, given by d
with a double pole break frequency at F
FIGURE 9. VOLTAGE-MODE BUCK CONVERTER
CIRCUIT
PWM
COMP
OUT
COMPENSATION DESIGN
MAX
HALF-BRIDGE
OSCILLATOR
/V
V
IN
COMP
OSC
E/A
DRIVE
V
at the LX node. The PWM wave is
IN
R
ISL8105B
2
/V
REF
. This function is dominated by a DC
C
+
OSC
-
VREF
2
C
, level. The error amplifier output
1
11
, and shaped by the output filter,
BOOT
FB
BGATE
TGATE
EXTERNAL CIRCUIT
LX
, as close as practical to
R
LC
OUT
3
V
IN
R
and a zero at F
1
) is regulated to
C
L
3
DCR
V
ESR
OUT
C
CE
ISL8105B
.
For the purpose of this analysis, C and ESR represent the total
output capacitance and its equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL8105B) and the external R
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
margin (better than +45°). Phase margin is the difference
between the closed loop phase at F
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R
C
poles and zeros of the compensation network:
It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. Equations 9 and 10 describe the
frequency response of the modulator (G
compensation (G
F
1. Select a value for R
2. Calculate C
3. Calculate C
4. Calculate R
LC
3
) in Figure 9. Use the following guidelines for locating the
value for R
setting the output voltage to be equal to the reference set
voltage as shown in Figure 9, the design procedure is
shown in Equation 5.
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
such that F
times F
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
R
C
C
R
C
=
2
1
2
3
3
---------------------------
2π
=
=
=
=
=
-------------------------------------------- -
d
---------------------------------------------- -
2π R
------------------------------------------------------- -
2π R
⋅
--------------------- -
F
----------- - 1
------------------------------------------------ -
2π R
F
V
MAX
1
SW
SW
LC
OSC
L C
0
R
⋅
⋅
⋅
; typically 0.1 to 0.3 of f
⋅
1
). F
2
–
1
2
2
2
P2
⋅
3
3
V
such that F
⋅
⋅
for desired converter bandwidth (F
⋅
such that F
such that F
⋅
1
FB
0.5 F
C
R
1
IN
C
SW
0.7 F
is placed below F
1
1
1
) and closed-loop response (G
⋅
⋅
⋅
LC
⋅
F
⋅
F
F
represents the regulator’s switching
LC
CE
0
LC
SW
1
(to adjust, change the 0.5 factor to
F
(1kΩ to 10kΩ, typically). Calculate
CE
–
Z1
P1
1
Z2
=
is placed at a fraction of the F
is placed at F
is placed at F
-------------------------------- -
2π C ESR
⋅
0dB
CE
SW
SW
1
1
⋅
, R
/F
) and adequate phase
and +180°. The
LC
(typically, 0.5 to 1.0
MOD
2
, R
, the lower the F
P2
LC
CE
1
LC
3
), feedback
to R
lower in
).
, C
.
. Calculate C
1
3
, C
, C
CL
April 15, 2010
0
). If
2
):
1
(EQ. 4)
(EQ. 5)
(EQ. 7)
FN6447.2
(EQ. 6)
(EQ. 8)
, and
to C
LC
Z1
3
3
,