ISL6559EVAL2 Intersil, ISL6559EVAL2 Datasheet - Page 2

• Manufacturer Part Number: ISL6559EVAL2
• Description: EVALUATION BOARD 2 ISL6559
• Manufacturer: Intersil

Specifications of ISL6559EVAL2

• Main Purpose: Special Purpose DC/DC, VRM Supply
• Outputs And Type: 1, Non-Isolated
• Power - Output: 67.6W
• Voltage - Output: 1.3V
• Current - Output: 52A
• Voltage - Input: 5V, 12V
• Regulator Topology: Buck
• Frequency - Switching: 250kHz
• Board Type: Fully Populated
• Utilized Ic / Part: HIP6601, ISL6559
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

number of active phases in the converter and is preset for
3-phase operation. JP2 is set with PHASE 3 in the ON
position. Before connecting the power supplies to the board,
place switches SW1 and SW2 in the OFF position.
Input Power Connections
Two ATX supply connections are provided on the
ISL6559EVAL2 board. The main ATX power connector
mates with the 20-pin header, J1, labeled ATX. The 12V
AUX power connector mates with a 4-pin header, J2, labeled
ATX12V. Insure both connections are secure and SW1 and
SW2 are in the OFF position before switching on the ATX
supply.
Three female-banana jacks are provided for connection of
bench-top supplies. Connect the +12V terminal to J3, +5V
terminal to J4, and the common ground to terminal J5. Turn
on the +5V supply first to energize the ENABLE and power
good circuitry, then turn on the +12V supply.
Once power is applied to the board, the PGOOD LED
indicator will begin to illuminate red. With SW1 in the OFF
position, the ENABLE input of the ISL6559 is held low and
the startup sequence is inhibited.
Power Output Connections
The ISL6559EVAL2 output can be exercised using either
resistive or electronic loads. Copper alloy terminal lugs
provide connection points for loading. Tie the positive load
connection to VCORE, terminal J6, and the negative to
ground, terminal J7. A shielded scope probe test point, TP8,
allows for inspection of the output voltage, VCORE.
Enabling the Controller
The state of VCC, EN, and FS/DIS dictate the beginning of a
soft-start interval. The FS/DIS pin is only used to set the per
phase switching frequency on the evaluation board. VCC is
tied to jumper JP1 which will arrive preset to +12V. Once the
input and output terminal connections are made, switch the
ENABLE switch (SW1) to the ON position. The EN signal is
released to rise above the ENABLE threshold of 1.23V
nominal. Once the ENABLE threshold is exceeded, a soft-
start interval is initiated. The output voltage will ramp in a
controlled manner with PGOOD changing from red to green
when the output voltage passes through the under-voltage
threshold.
If JP1 is placed in the +5V position, the internal regulator of
the controller is disabled. The controller and drivers now are
enabled from two different sources. To prevent the controller
from enabling before the HIP660X drivers are active, the
threshold sensitive EN pin is used for power sequencing
between the controller and drivers. A resistor divider from
the +12V input is connected to EN. The resistors are
selected such that the ISL6559 enable threshold is reached
after the VCC rising threshold has been exceeded on all the
HIP6601 drivers.
2
Application Note 1137
On-Board Load Transient Generator
Most bench-top electronic loads are not capable of
producing the current slew rates required to emulate modern
microprocessors. For this reason, a discrete transient load
generator is provided on the evaluation board, see Figure 1.
The generator produces a load pulse of 112µs in duration
with a period of 14.5ms. The pulse magnitude is
approximately 20A, with rise and fall slew rates of
approximately 30A/µs as configured. The short load current
pulse and long duty cycle is required to limit the power
dissipation in the load resistors (R34-R38) and MOSFETs
(Q7, Q8). To engage the load generator, place switch SW2
in the ON position.
If the DAC code is changed from 01010 (1.300V), the
transient generator dynamics must be adjusted to the new
output voltage level. Place a scope probe in TP9 to measure
the voltage across the load resistors and the dv/dt across
them as well. Adjust the load resistors, R34-R38, to achieve
the correct load current level. Change resistors R30-R33 to
increase or decrease the dv/dt, as required, to match the
desired di/dt profile.
ISL6559 VRD Performance
Soft-Start Interval
The typical start-up waveforms for the ISL6559EVAL2 are
shown in Figure 2. The DAC is set to 01010 (1.300V) and
the converter is started into a 52A load. The ENABLE switch,
SW1, is thrown to the ON position and the voltage on EN
VCC12
VCORE
HUF76129
R37
DNS
46.4kΩ
R28
Q7
FIGURE 1. LOAD TRANSIENT GENERATOR
R35
0.100Ω
C61
1µF
HUF76129
R34
0.500Ω
Q8
M3
2N7002
U5
VSS
HS
402Ω
R36
0.200Ω
R29
HIP2100
BAV99LT1
BAV99LT1
D1
D2
R38
DNS
HO
LO
C62
10µF
453Ω
1.05kΩ
453Ω
1.05kΩ
R33
R30
R31
R32
VLOAD
TP9
SW2
ON
OFF