ISL6559EVAL2 Intersil, ISL6559EVAL2 Datasheet - Page 4

• Manufacturer Part Number: ISL6559EVAL2
• Description: EVALUATION BOARD 2 ISL6559
• Manufacturer: Intersil

Specifications of ISL6559EVAL2

• Main Purpose: Special Purpose DC/DC, VRM Supply
• Outputs And Type: 1, Non-Isolated
• Power - Output: 67.6W
• Voltage - Output: 1.3V
• Current - Output: 52A
• Voltage - Input: 5V, 12V
• Regulator Topology: Buck
• Frequency - Switching: 250kHz
• Board Type: Fully Populated
• Utilized Ic / Part: HIP6601, ISL6559
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

1.30V
20A
transient load current. As the load is removed, the output
voltage rises in response. The controller detects the load
change and immediately decreases the channel duty cycles.
The duty cycle of PWM1 is reduced to zero for one cycle as
those of the other two channels are notably reduced. During
this time, the inductors quickly shed load current, and once
again reduce the amount of capacitance required to supply
the load. The core voltage returns to the no-load offset level
of 1.320V.
Over-Current Protection
The ISL6559 monitors the output current level by averaging
the sampled current from each ISEN pin. The R
resistors (R1, R2, R3) are selected so that the current
sourced by the ISEN pins, at maximum load current, is
50µA. The average of the sampled currents is compared
with an over-current trip level of 90µA. Once the average
current meets or exceeds the OC reference current, the
controller immediately places all PWM signals in a high-
impedance state, quickly removing gate drive to the
HIP6601B drivers, and forcing the core voltage to decay as
the output capacitors discharge. The PGOOD signal
transitions low when the core voltage drops below the UV
threshold.
After the over-current event is detected, the controller waits
a short delay time before initiating a soft-start interval to
allow the disturbance to clear. The delay time is equivalent to
the soft-start interval and is 8.3ms, for this design. If during
the soft-start interval another over-current trip is detected,
the PWM signals are again placed in a high impedance state
0V
0V
0A
0V
PWM2, 10V/DIV
PWM3, 10V/DIV
PWM1, 10V/DIV
FIGURE 4. FALLING EDGE TRANSIENT RESPONSE
5µs/DIV
4
LOAD CURRENT, 10A/DIV
VCORE, 50mV/DIV
I
L1
, 5A/DIV
I
L2
, 5A/DIV
I
L3
, 5A/DIV
ISEN
Application Note 1137
1.0V
0V
0V
0V
and PGOOD remains low. The controller waits another
8.3ms before another soft-start interval is attempted. This
hiccup mode of operation repeats up to seven times, with the
eighth prompting the converter to latch off.
Figure 5 shows the hiccup mode operation of the converter
when a hard short is applied across the output terminals of
the evaluation board. The converter quickly places the PWM
signals in a high-impedance state and the core voltage
decays quickly. The short is not removed, resulting in the
controller latching off after the seventh attempt.
0A
VID on the Fly
The AMD Hammer Family microprocessors can change VID
inputs at any time while the regulator is in operation. The
power management solution is required to monitor the DAC
inputs, and respond to VID voltage transitions in a controlled
manner, supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption. The ISL6559 checks the five VID inputs at the
beginning of each switching cycle. If the VID code has
changed, the controller waits one complete switching cycle
to validate the new code. If the new code is stable during this
one cycle delay, then the controller begins incrementing the
reference voltage toward the new DAC code in 25mV steps,
every two switching-cycles, until the new DAC code is
reached.
Figure 6 shows a 250mV DAC change prompted by
changing VID3 and VID1 simultaneously. Originally, at
1.550V (00000), the core voltage ramps down to the new
DAC setting of 1.300V (01010). The VID-on-the-Fly
transition is completed in 80µs, well within the 100µs
maximum window allowed. The converter is supporting a
26A load during the transition. The PGOOD signal is steady
throughout the DAC change and indicates no operational
problems are encountered.
FIGURE 5. OVER-CURRENT PROTECTION
LOAD CURRENT, 20A/DIV
VCORE, 1V/DIV
PWM3, 10V/DIV
PWM1, 10V/DIV
PWM2, 10V/DIV
10ms/DIV