CDB4344 Cirrus Logic Inc, CDB4344 Datasheet - Page 14

• Manufacturer Part Number: CDB4344
• Description: BOARD EVAL FOR CS4344 DAC
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r

Specifications of CDB4344

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 2, Single Ended
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 85°C
• Utilized Ic / Part: CS4344
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS4344
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1006

14
Right Justified, 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
SDATA
SDATA
LRCK
LRCK
SCLK
SCLK
0
Internal SCLK Mode
Internal SCLK Mode
23 22 21 20 19 18
15 14 13 12 11 10
32 clocks
32 clocks
Left Channel
Left Channel
Figure 10. CS4348 Data Format (Right Justified 16)
Figure 9. CS4346 Data Format (Right Justified 24)
9 8 7
7
6 5 4 3 2 1 0
6 5 4 3 2 1 0
Right Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
23 22 21 20 19 18
15 14 13 12 11 10
External SCLK Mode
External SCLK Mode
Right Channel
Right Channel
9 8 7
7
6 5 4 3 2 1 0
6 5 4 3 2 1 0
CS4344/5/6/8
DS613F1