CYIL2SM1300-EVAL Cypress Semiconductor Corp, CYIL2SM1300-EVAL Datasheet
CYIL2SM1300-EVAL
Specifications of CYIL2SM1300-EVAL
Related parts for CYIL2SM1300-EVAL
CYIL2SM1300-EVAL Summary of contents
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... MSPS. On-chip digital column Ordering Information Marketing Part Number CYIL2SM1300AA-GZDC CYIL2SM1300AA-GWCES CYIL2SC1300AA-GZDC CYIL2SM1300-EVAL Note 1. Contact your local sales office for the windowless option. Cypress Semiconductor Corporation Document Number: 001-24599 Rev. *C LUPA 1300-2: High Speed CMOS FPN correction enables the sensor to output ready to use image data for most applications ...
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... It requires only one master clock for operation up to 500 fps. The sensor is available in a monochrome version or Bayer (RGB) patterned color filter array placed in a 168-pin ceramic µPGA package. Document Number: 001-24599 Rev. *C CYIL2SM1300AA Specifications Table 1. General Specifications Parameter Specifications Active Pixels ...
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... Photovoltaic Response Curve Figure 2. Photo Voltaic Response of LUPA 1300-2 Spectral Response Curve Document Number: 001-24599 Rev. *C Figure 3. Spectral Response of LUPA 1300-2 CYIL2SM1300AA Page [+] Feedback ...
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... Figure 4. Spectral Response of LUPA 1300-2 Color Sensor 0.2 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 400 500 Document Number: 001-24599 Rev. *C 600 700 800 CYIL2SM1300AA RED GREEN NEAR RED GREEN NEAR BLUE BLUE 900 1000 Page [+] Feedback ...
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... Shutdown mode, lux=0 Clock enabled, lux=0 transient duration=9 µs transient duration=2.5 µs Shutdown mode, lux=0 Clock enabled, lux=0 Clock enabled, lux=0 Shutdown mode, lux=0 Clock enabled, lux=0 Clock enabled, lux=0 Shutdown mode, lux=0 CYIL2SM1300AA Unit Min Max s -0.5 5.5 V -0.5 5.5 V ...
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... Unused inputs must always be tied to an appropriate logic level, for example ground through a 100 nF capacitor. The recommended combinations of supplies are: ■ Analog group of +2.5V supply ADC pix ■ Digital Group of +2.5V supply: V CYIL2SM1300AA Min Typ Max -5% 2.5 + 0.1 -5% 2.5 +5% 2 ...
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... Figure 5. Floor Plan of the Sensor Image core 1280 x 1024 31.5 Msps Clk X & Clk Y Analog front end 31.5 Msps 31.5 MHz Local register Data block 63 Msps LVDS TX and RX 12x LVDS outputs at 630 Msps CYIL2SM1300AA Typ Units 400 mW 1350 mW Typ Max Units 315 MHz 50 ...
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... The unity gain selection of the PGA is done by the default afemode<5:3> setting. Table 10. Gain Settings afemode<5:3> 000 001 010 011 12 channels 100 101 CYIL2SM1300AA on page 10 discusses the use of Frame Rate Frame Read (fps) Out Time (µs) 507 1970 1842 550 6933 ...
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... Sequencer reset, active LOW System clock (630 MHz) SPI chip select Clock of the SPI Data line of the SPI, serial input Data line of the SPI, serial output Figure 7. Synchronous Shutter Operation Burst Readout ti CYIL2SM1300AA Image Sensor Timing and Readout on page 18. Time axis Page [+] Feedback ...
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... Reserved, fixed value 1 [7:0] 0xFF Reserved, fixed value 2 [7:0] 0x00 Reserved, fixed value 3 [7:0] 0x00 Reserved, fixed value 4 [7:0] ‘0x08’ Reserved, fixed value CYIL2SM1300AA time Table 12 on page 10 summarizes the Disadvantages Detailed Description of Internal Registers Description Page [+] Feedback ...
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... Bias pixel precharge level [7:4] ‘1000’ Bias column ota 19 [3:0] ‘1000’ Bias column unip fast [7:4] ‘1000’ Bias column unip slow 20 [3:0] ‘1000’ Bias column load [7:4] ‘1000’ Bias column precharge CYIL2SM1300AA Description Page [+] Feedback ...
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... Bypass the data block [1] 0 Enables the FPN correction [2] 0 Overwrite incoming ADC data by the data in the testpat register [3] 0 Reserved, fixed value [5:4] 0x00 Pattern inserted to generate a test image 55 [7:0] 0x00 Pattern inserted to generate a test image CYIL2SM1300AA Description Page [+] Feedback ...
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... Expressed in number of lines ‘1’: Expressed in clock cycles (multiplied by 2**seqmode4[3:0]) [7] 0 Allows delaying the syncing of events that happen outside of ROT to the next ROT. This avoids image artefacts. CYIL2SM1300AA Description Page [+] Feedback ...
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... Length of integration time (granularity selectable) [7:0] 0x40 Length of DS integration time (granularity selectable) [1:0] 0x00 Length of DS integration time (granularity selectable) [7:0] 0x0C Length of TS integration time (granularity selectable) [1:0] 0x00 Length of TS integration time (granularity selectable) CYIL2SM1300AA Description Page [+] Feedback ...
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... ADCs to one LVDS block and performs some minor data handling: ■ CRC calculation and insertion ■ Training and test pattern generation The most important registers in this block are: Dataconfig. The dataconfig1[7:6] and dataconfig2[7:0] registers insert a training pattern in the LVDS channels to sync the LVDS receivers. CYIL2SM1300AA Description Page [+] Feedback ...
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... X4_start (73, 6bit). This register sets the X start address for window 4 (if enabled). Y4_end (74 and 75, 10 bit). These registers set the Y end address for window 4 (if enabled). X4_kernels (75, 6 bit). This register sets the number of kernels or X width to be read out for window 4 (if enabled). CYIL2SM1300AA Page [+] Feedback ...
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... SPI uploads stored on the chip. The SPI clock speed must be slower by a factor of 30 when compared to the system clock (315 MHz nominal speed). Figure 9. Write Access (C='1') Figure 10. Read Access (C='0') CYIL2SM1300AA Figure 9 and Page [+] Feedback ...
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... SPI selects between the master and slave modes. Figure 11. Global Readout Timing (Parallel) Integration frame I+2 Readout frame I+1 Readout Lines L2 L1024 ... K2 ... K54 Readout Pixels Reset Reset N Exposure Time N N+1 Readout N-1 FOT FOT ROT Line Readout CYIL2SM1300AA Exposure Time Readout N Page [+] Feedback ...
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... Ensure that the added value of the registers res_length and tint_timer always exceeds the number of lines that are read out. This is because the sequencer samples a new image after integration is complete, without checking if image readout is finished. Enlarging res_length to accommodate for this has no impact on image capture. Document Number: 001-24599 Rev. *C CYIL2SM1300AA Page [+] Feedback ...
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... Synchronize external flash with exposure ■ Apply extremely long integration times (only in slave mode) Document Number: 001-24599 Rev. *C Figure 14. When the input pin int_time is asserted, the pixel Exposure Time N Reset FOT FOT Readout N CYIL2SM1300AA Reset Read out N+1 N+1 Page [+] Feedback ...
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... This value must be written to the windowX_3 and windowX_4 register. In case of windowing, the effective readout time is smaller than in full frame mode, because only the relevant part of the image array is accessed result possible to achieve higher frame rates. CYIL2SM1300AA 1024 pixels Page [+] Feedback ...
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... Figure 18. Multiple Windows Read from the Same Pixel Array Document Number: 001-24599 Rev result, the line numbers always increment. When reverse scanning in X, the Figure 17. Normal and Reverse Scanning in Y CYIL2SM1300AA Figure 18 shows how to configure two Page [+] Feedback ...
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... Figure 20 By choosing the time stamps of the double and triple slope resets (typical at 90% and 99% of the integration, configurable by the user possible to have a nonsaturated pixel value even for pixels that receive a huge amount of light. CYIL2SM1300AA Exposure Time Readout N Window 2 t Page ...
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... You must configure the multiple slope parameters for the application and interpret the pixel data accordingly. Document Number: 001-24599 Rev. *C Figure 21. Triple Slope Timing in Master Mode Figure 22. Triple Slope Timing in Slave Mode CYIL2SM1300AA Page [+] Feedback ...
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... The registers used to configure the correction are: Figure 23. Dark Image Without FPN Correction (5x Amplified) Figure 24. Dark Image With FPN Correction Enabled (5x Amplified) Document Number: 001-24599 Rev. *C CYIL2SM1300AA ■ datachannelX_1 with X from 0 to 11. The field [1] of these registers enables the offset corrections of the specific output channel ...
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... Pixels are always read in multiples of 24 (one value to every channel in the AFE). The last time slot contains not only valid pixels, but also two dummy columns, six grey columns, and eight black columns. Document Number: 001-24599 Rev. *C Figure 25. Before the actual pixels are read out, one dummy Figure 25. Sensor Read Out Format CYIL2SM1300AA Page [+] Feedback ...
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... FPN stored values FPN Normal Data Training Pattern Document Number: 001-24599 Rev. *C Table 15. Note that a FS also serves as LS, and vice versa. Figure 26. Data and Sync Channel Overview 10-Bit Code 0x059 0x056 0x05A 0x055 0x0A9 0x0A6 0x13C D 0x193 T T CYIL2SM1300AA Page [+] Feedback ...
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... Sync Channel T Document Number: 001-24599 Rev. *C Figure 25 on page 26 is read out. Figure 27. Full Frame Mode Read Out black ROT line 0 line 1 ROT timeslot timeslot timeslot CYIL2SM1300AA Figure 27 shows the internal state of the line ROT line 1022 1023 timeslot timeslot CRC ...
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... CYIL2SM1300AA ch8 ch9 ch10 ch11 ...
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... Sequencer internal state Data Channel Sync Channel Data Channel Sync Channel Document Number: 001-24599 Rev. *C Line FOT ROT black ROT ROT line Ys Ys timeslot timeslot timeslot X X+1 53 CYIL2SM1300AA Figure 28. A clear distinction is made with line Ye ROT timeslot CRC timeslot 54 Page [+] Feedback ...
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... Although the window is defined as not containing Figure 29 on page 30 and Figure 31. black line Ys line FOT ROT ROT ROT Ys timeslot timeslot timeslot timeslot Xstart Xend-1 54. The dummy black line again spans the entire width of CYIL2SM1300AA line Ye ROT timeslot CRC Xend 54 timeslot Single Window Mode Containing Page [+] Feedback ...
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... C 133 132 129 126 123 120 117 114 111 108 105 102 135 139 140 137 145 * 5 U 136 144 141 138 146 * 8 V 149 147 142 * 150 148 143 * Document Number: 001-24599 Rev TOP VIEW CYIL2SM1300AA Page [+] Feedback ...
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... ADC ground I/O ADC power I/O LVDS power O p output channel [ output channel [ output channel [10 output channel [10 output channel [11 output channel [11] not assigned not assigned I/O LVDS ground I/O ADC ground CYIL2SM1300AA Position V10 W10 T10 U11 T11 U10 V11 W11 ...
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... I DFT scan enable I DFT clock I DFT clock enable I/O pixel core ground I/O digital ground I/O digital power supply I/O pixel core supply CYIL2SM1300AA Position T17 U18 V19 W19 V20 W20 W24 V24 W22 V22 U20 T20 U22 ...
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... I/O digital ground I/O pixel core ground not assigned not assigned not assigned not assigned O ADC common mode decoupling I/O pixel core supply O ADC black reference decoupling CYIL2SM1300AA Position A18 C17 B17 A17 C16 B16 A16 C15 B15 A15 C14 B14 ...
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... I/O column buffers supply I/O column buffers ground I/O digital ground I/O ADC power supply I/O ADC ground I/O higher limit ADC range decoupling I/O lower limit ADC range decoupling I/O digital power supply I/O digital ground CYIL2SM1300AA Position ...
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... Package Information Figure 32. Package Outline Drawing with Glass The total distance from the bottom of the µPGA package (same as the PCB plane) to the top of the die surface is 19.016 mm. Document Number: 001-24599 Rev. *C CYIL2SM1300AA 001-44705 ** Page [+] Feedback ...
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... Package with Glass Cross Section Document Number: 001-24599 Rev. *C Figure 33. Pixel Active Area Dimensions Figure 34. Package Cross Section CYIL2SM1300AA Page [+] Feedback ...
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... Die Specifications 1450 ± Document Number: 001-24599 Rev. *C Figure 35. Die Specifications 1700 ± CYIL2SM1300AA Page [+] Feedback ...
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... AN54468: Interfacing the LUPA1300-2 with FPGA. This application note describes the interface between the LUPA 1300-2 and the FPGA, as implemented in the LUPA 1300-2 demonstration kit CYIL2SM1300-EVAL. It also provides an overview of the architecture of the demonstration kit and the method used to synchronize channels. ■ ...
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... Document History Page Document Title: CYIL2SM1300AA LUPA 1300-2: High Speed CMOS Image Sensor Document Number: 001-24599 Revision ECN Orig. of Change ** 1438663 FPW *A 2649816 NVEA/AESA *B 2745961 NVEA/AESA *C 2765859 NVEA/AESA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress offers standard and customized CMOS image sensors for consumer as well as industrial and professional applications. ...