DK-MAXII-1270N Altera, DK-MAXII-1270N Datasheet - Page 19

KIT DEV MAXII W/EPM 1270N

DK-MAXII-1270N

Manufacturer Part Number
DK-MAXII-1270N
Description
KIT DEV MAXII W/EPM 1270N
Manufacturer
Altera
Series
MAX® IIr
Type
CPLDr
Datasheets

Specifications of DK-MAXII-1270N

Contents
Dev Board, Quartus®II Web Edition, Nios®II Web Edition, Cables, Accessories, Reference Designs and Demos
Silicon Manufacturer
Altera
Core Architecture
CPLD
Core Sub-architecture
MAX
Silicon Core Number
EPM
Silicon Family Name
MAX II
Rohs Compliant
Yes
For Use With/related Products
MAX®II CPLDs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2380

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DK-MAXII-1270N
Manufacturer:
ALTERA
0
Altera Corporation
July 2005
V_INT shows the Core V
by POT1. ACTIVE_IO is driven by a MAX II user I/O pin that helps
demonstrate the instant MAX II becomes functional (powered-up and
configured).
Figure 2–4
V
minimum V
core V
V
1
In
test point on the board), switches to 0 V when V
switches after configuration is complete and the core registers are reset,
and released and the I/O are released. Once working, this I/O pin will
begin to oscillate with a high and low period equal to T
needed to move the configuration data from the Configuration Flash
Memory (CFM) to the configuration SRAM. The first falling edge on this
I/O (shown in the lighter color in
complete. Measuring back the T
Active I/O will show at approximately what core voltage configuration
started.
CCINT
CCIO
Figure
CC
level.
rise time is 10 ms. The device is functional at 2.18 V, well below the
Development Kit Version 1.1.0
of 1.25 V the I/O pull-up becomes active and the I/O goes to the
In the development board setup, the V
supply than V
not power cycle when S5 is pressed.
2–4, the MAX II representative I/O (labeled Active I/O on the
shows a typical digital oscilloscope output. For this test the
CC
level of 3.0 V. The I/O Pin starts out low, and at about a
CCINT
MAX II Development Kit Getting Started User Guide
CC
rise time, and the rise time variation caused
. The V
CONFIG
Figure
CCIO
of the first low pulse width of this
ring is a constant 3.3 V and does
2–4) is when configuration is
CCIO
CCINT
ring is on a different
is at 2.18 V. It
CONFIG
Getting Started
, the time
2–11

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