ADZS-BF527-EZLITE Analog Devices Inc, ADZS-BF527-EZLITE Datasheet - Page 58

• Manufacturer Part Number: ADZS-BF527-EZLITE
• Description: BOARD EVAL ADSP-BF527
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: DSPr

Specifications of ADZS-BF527-EZLITE

• Featured Product: Blackfin® BF50x Series Processors
• Contents: Evaluation Board
• Silicon Manufacturer: Analog Devices
• Core Architecture: Blackfin
• Features: USB-based, PC-hosted Tool Set
• Silicon Core Number: ADSP-BF527
• Silicon Family Name: Blackfin
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-BF522/523/524/525/526/527
HOSTDP A/C Timing- Host Read Cycle
Table 48
requirements.
Table 48. Host Read Cycle Timing Requirements
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
NM (Not Measured) — This parameter is not measured, because the time for which HOST_ACK is low is system design dependent.
SADRDL
HADRDH
RDWL
RDWL
RDWH
DRDHRDY
SDATRDY
DRDYRDL
RDYPRD
DDARWH
ACC
HDARWH
describe the HOSTDP A/C Host Read Cycle timing
HOST_ADDR and HOST_CE Setup
before HOST_RD falling edge
HOST_ADDR and HOST_CE Hold
after HOST_RD rising edge
HOST_RD pulse width low
(ACK mode)
HOST_RD pulse width low
(INT mode)
HOST_RD pulse width high or time
between HOST_RD rising edge and
HOST_WR falling edge
HOST_RD rising edge delay after
HOST_ACK rising edge (ACK mode)
Data valid prior HOST_ACK rising
edge (ACK mode)
Host_ACK assertion delay after
HOST_RD/HOST_CE (ACK mode)
HOST_ACK low pulse-width for
Read access (ACK mode)
Data disable after HOST_RD
Data valid after HOST_RD falling
edge (INT mode)
Data hold after HOST_RD rising
edge
HOST_ADDR
HOST_D15-0
HOST_CE
HOST_ACK
HOST_RD
1.5 t
t
t
2 t
DRDYRDL
t
RDYPRD
DRDHRDY
+ 8.7
Min
V
2.5
4.5
1.0
Rev. PrG | Page 58 of 80 | February 2009
4
0
DDEXT
t
SCLK
SADRDL
Figure 33. HOSTDP A/C- Host Read Cycle
SCLK
+
+
t
ADSP-BF522/524/526,
DRDYRDL
= 1.8 V
1.5 t
1.5 t
Max
NM
9.0
SCLK
1
SCLK
t
SDATRDY
t
ACC
1.5 t
t
t
t
RDYPRD
V
DRDYRDL
2 t
t
t
RDYPRD
DRDHRDY
RDWL
+ 8.7
DDEXT
Min
2.5
3.5
1.0
4
0
SCLK
SCLK
+
+
= 2.5/3.3 V
1.5 t
1.5 t
t
DRDHRDY
t
Max
NM
HDARWH
9.0
1
SCLK
SCLK
t
HADRDH
t
RDWH
1.5 t
t
t
2 t
DRDYRDL
t
RDYPRD
DRDHRDY
+ 8.7
Min
V
2.5
4.5
1.0
t
4
0
DDARWH
DDEXT
Preliminary Technical Data
SCLK
SCLK
+
+
ADSP-BF523/525/527
= 1.8 V
1.5 t
1.5 t
Max
NM
9.0
1
SCLK
SCLK
1.5 t
t
t
2 t
V
DRDYRDL
t
RDYPRD
DRDHRDY
+ 8.7
DDEXT
Min
2.5
3.5
1.0
4
0
SCLK
SCLK
+
= 2.5/3.3 V
+
1.5 t
1.5 t
Max
NM
9.0
SCLK
1
SCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns