DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 17
![KIT DEV CYCLONE III LS EP3CLS200](/photos/9/24/92409/dk-dev-3cls200n_sml.jpg)
DK-DEV-3CLS200N
Manufacturer Part Number
DK-DEV-3CLS200N
Description
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer
Altera
Series
Cyclone® IIIr
Type
FPGAr
Datasheets
1.EP3C5F256C8N.pdf
(34 pages)
2.EP3C5F256C8N.pdf
(14 pages)
3.DK-START-3C25N.pdf
(74 pages)
4.DK-DEV-3CLS200N.pdf
(42 pages)
Specifications of DK-DEV-3CLS200N
Contents
Board
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Cyclone
Silicon Core Number
EP3C
Silicon Family Name
Cyclone III LS
Rohs Compliant
Yes
For Use With/related Products
EP3CLS200
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2601
1
2
See supported protocols and data rates on page 63
Implemented in HCells.
Since all HardCopy ASICs contain hard-wired logic, they are inherently secure.
Usable ASIC gates
Equivalent LEs
M9K memory blocks
M144K memory blocks
MLAB memory
Embedded memory (Kb)
18-bit x 18-bit multipliers
PLLs/unique outputs
Design security
Stratix series
prototyping support
I/O voltage levels supported (V)
I/O standards supported
Emulated LVDS channels
1,100 Mbps
LVDS channels, 1,250 Mbps
(receive/transmit)
Embedded DPA circuitry
Series and differential OCT
Transceiver (SERDES) channels, 6.5
Gbps/6.5 Gbps PMA only
PCIe hard IP blocks
Memory devices supported
2
1
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
HC4GX15
353,600
9,396
1,288
28/28
9.4M
3/27
660
184
8/0
24
1
Differential SSTL-18, Differential SSTL-2,Differential HSTL-12, Differential HSTL-15,
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15,
Differential HSTL-18, SSTL-15 (I and II), SSTL-18 (I and II), SSTL-2 (I and II),
1.2-V HSTL (I and II), 1.5-V HSTL (I and II), 1.8-V HSTL (I and II)
HardCopy IV ASICs (0.9 V), 6.5-Gbps Transceivers
EP4SGX110
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
HC4GX25
531,600
13,608
11.5M
1,288
44/44
6/54
16/8
936
236
36
DDR3, DDR2, DDR, QDR II, RLDRAM II, SDR
2
Implemented in HCells
1.2, 1.5, 1.8, 2.5, 3.0
Altera Product Catalog
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
HC4GX35
531,600
20,736
11.5M
1,280
1,288
88/88
24/12
8/68
280
64
3
3
3
2
HardCopy IV ASIC Features
EP4SE230
EP4SE360
•
HC4E25
353,600
12,384
1,288
56/56
9.4M
4/34
2011
864
120
32
—
—
•
www.altera.com
EP4SE360
EP4SE530
EP4SE820
HC4E35
813,050
18,792
1,320
1,040
12/96
88/88
Devices
15M
216
48
—
—
15