ATEVK1104S Atmel, ATEVK1104S Datasheet - Page 46

KIT EVAL FOR AT32UC

ATEVK1104S

Manufacturer Part Number
ATEVK1104S
Description
KIT EVAL FOR AT32UC
Manufacturer
Atmel
Series
AVR®32 UC3r
Type
MCUr
Datasheets

Specifications of ATEVK1104S

Contents
Board, Cables
Tool Type
Development Kit
Cpu Core
AVR 32
Data Bus Width
32 bit
Processor Series
AT32
Processor To Be Evaluated
AT32UC3A3256S
Interface Type
USB, JTAG, SD Card, Nexus, MMC
Core Architecture
AVR
Operating Supply Voltage
5.5 V
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
9. Boot Sequence
9.1
9.2
32072C–AVR32–2010/03
Starting of Clocks
Fetching of Initial Instructions
This chapter summarizes the boot sequence of the AT32UC3A3/A4. The behavior after power-
up is controlled by the Power Manager. For specific details, refer to
(PM)” on page
After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the
power has stabilized throughout the device. Once the power has stabilized, the device will use
the internal RC Oscillator as clock source.
On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have
a divided frequency, all parts of the system receives a clock with the same frequency as the
internal RC Oscillator.
After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset
address, which is 0x8000_0000. This address points to the first address in the internal Flash.
The code read from the internal Flash is free to configure the system to use for example the
PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the
clocks to unused peripherals.
39.
AT32UC3A3/A4
Section 9. ”Power Manager
46

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