Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 16

KIT DEVELOPMENT F083A

Z8F083A0128ZCOG

Manufacturer Part Number
Z8F083A0128ZCOG
Description
KIT DEVELOPMENT F083A
Manufacturer
Zilog
Series
Z8 Encore! XP®r
Type
MCUr
Datasheets

Specifications of Z8F083A0128ZCOG

Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F083A
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4672

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8F083A0128ZCOG
Manufacturer:
Zilog
Quantity:
1
PRS001003-1207
3. For information block programming, ADDR [13:7] are don’t care. ADDR [6:0] are
4. If you do not follow the timing spec such as Tnvs and Tprec, it may cause fatal
5. No recovery time required from standby to first read and first program.
6. All input waveforms are with rising time (tr) and falling time (tf) of 1 ns. The capacitor
7. Access time (Tae) is measured with 0.1 pF loading capacitance
8. Tdf means data hold time from the end of Tcyc. Output data will not be valid after Tdf.
Sector Erase Operation Timing
The main memory block is organized into twenty-four 4 K bits uniform sectors. The
information block contains one single sector of 1 Kb. A Sector Erase operation allows
erasing any individual sector. Pre-programming the sector is not required prior to Sector
Erase operation. CE, AE, SERA, NVSTR, and IFREN signals activate a Sector Erase
operation. The sector addresses are latched on the rising edge of SERA.
The Sector Erase operation is similar to Mass Erase operation except the addresses; and
IFREN will be used to select the sector for erasure. Each Sector Erase operation erases one
sector at a time. The IFREN signal determines whether to erase a sector in main memory
block or information block. If IFREN is pulled low (VIL), the main memory sector will be
erased. Similarly, if IFREN is pulled high (VIH), the information block will be erased. The
internal erasure voltages and timing is controlled by NVSTR signal.
Sector Erase operation timing.
used to select one column in each I/O within the information block.
damage.
loading for all the eFlash macro input pin is 0.5 pF.
Z8 Encore!
Figure 9
®
F083x Series
Page 16 of 25
displays the

Related parts for Z8F083A0128ZCOG