C8051F411EK Silicon Laboratories Inc, C8051F411EK Datasheet - Page 100
![KIT EVAL FOR C8051F411](/photos/9/25/92547/c8051f411ek_sml.jpg)
C8051F411EK
Manufacturer Part Number
C8051F411EK
Description
KIT EVAL FOR C8051F411
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F411EK
Contents
Evaluation Board, CD-ROM, USB Cable, Batteries and User Guide
Processor To Be Evaluated
C8051F41x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F411
Silicon Family Name
C8051F41x
Kit Contents
LCD Based Evaluation Board, USB Cable, Software CD And Quick-Start Guide
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F41x
For Use With
336-1315 - KIT REF DESIGN VOICE RECORD F41X
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1317
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C8051F410/1/2/3
100
Bit7:
Bit6:
Bit5:
Bits4–3: RS1–RS0: Register Bank Select.
Bit2:
Bit1:
Bit0:
R/W
CY
Bit7
CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to 0 by all other arithmetic operations.
AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
These bits select which register bank is used during register accesses.
OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum
is even.
RS1
0
0
1
1
R/W
AC
Bit6
SFR Definition 10.4. PSW: Program Status Word
RS0
0
1
0
1
R/W
Bit5
F0
Register Bank
RS1
R/W
Bit4
0
1
2
3
Rev. 1.1
RS0
R/W
Bit3
0x00–0x07
0x08–0x0F
0x10–0x17
0x18–0x1F
Address
R/W
OV
Bit2
R/W
Bit1
F1
SFR Address: 0xD0
PARITY
Bit0
R
00000000
Addressable
Reset Value
Bit
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