MPC8349E-MITX-GP Freescale Semiconductor, MPC8349E-MITX-GP Datasheet - Page 25

• Manufacturer Part Number: MPC8349E-MITX-GP
• Description: KIT REFERENCE PLATFORM MPC8349E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8349E-MITX-GP

• Contents: Module and Misc Hardware
• For Use With/related Products: MPC8349E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.6.4.1
CLKIN is the input to the CCB PLL to generate the CCB clock, which provides the platform logic.
Table 16
ratios.
Freescale Semiconductor
18–19
20–27
Bits
28
29
30
31
shows the common combinations of CLKIN, CCB, and the core frequency and their respective
Reset Configuration Word SPMF[0–3] and COREPLL[0–6]
Table 15. Reset Configuration Word High (RCWH) Bit Descriptions (continued)
66.666 MHz
66.666 MHz
66.666 MHz
66.666 MHz
66.666 MHz
66.666 MHz
66.666 MHz
66.666 MHz
66.666 MHz
Reserved
Reserved
TSEC2M
Name
CLKIN
LALE
LDP
TLE
MPC8349E-mITX-GP Reference Design Platform User’s Guide, Rev. 0
0101
0100
0011
0101
0100
0011
0101
0100
0011
SPMF
[0–3]
TSEC2 Mode
—
True little endian
Local Bus ALE
signal timing
LDP/CKSTP pin
mux state after
reset
—
Preliminary—Subject to Change Without Notice
Meaning
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
CCB
Table 16. Core PLL Ratio
CLKIN
clock:
Ratio
CCB
5:1
4:1
3:1
5:1
4:1
3:1
5:1
4:1
3:1
00
01
10: Default
10
Must be cleared
0: Default
1
0: Default
1
0: Default
1
Must be cleared
COREPLL
00 0010 0 667 MHz
00 0010 1 667 MHz
00 0010 0 600 MHz
01 0001 1 500 MHz
00 0010 0 533 MHz
00 0010 1 500 MHz
00 0001 0
01 0001 1 400 MHz
01 0010 0 400 MHz
[0–6]
RGMII
RTBI
GMII
TBI
Big-endian mode
True little endian mode
Normal LALE timing
LALE is negated 1/2 lbiu_controller_clk earlier.
LDP[0] and
LDP[1] = local data parity.
LDP[0] = CKSTOP_OUT and LDP[1] =
CKSTOP_IN.
333 MHz
Frequency
Detailed Description
Core
CLKIN Ratio
CCB Clock:
2.5:1
1.5:1
2.5:1
1.5:1
2:1
3:1
2:1
1:1
2:1
MPC8349E-mITX-GP Board
25