MPC8377E-RDBA Freescale Semiconductor, MPC8377E-RDBA Datasheet - Page 111

• Manufacturer Part Number: MPC8377E-RDBA
• Description: BOARD REF DES MPC8377 REV 2.1
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8377E-RDBA

• Design Resources: MPC8379E-RDB Ref Design Guide
• Contents: Board, CD
• Frequency: 667 MHz
• For Use With/related Products: MPC8377E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2
23.2
RCWLR[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the
e300 core clock (core_clk).
that are not listed in
Freescale Semiconductor
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
CFG_CLKIN_DIV
0–1
nn
11
00
01
10
00
01
at reset
Low
Low
Low
Low
Low
Low
Low
Low
Low
Core PLL Configuration
RCWLR[COREPLL]
1
Core VCO frequency = core frequency × VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the
range of 800–1600 MHz.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Table 79
nnnn
0000
0001
0001
0001
0001
0001
2–5
Table 78. CSB Frequency Options for Agent Mode (continued)
SPMF
Table 79
0111
1000
1001
1010
1011
1100
1101
1110
1111
should be considered as reserved.
Table 79. e300 Core PLL Configuration
6
0
n
0
0
0
1
1
shows the encodings for RCWLR[COREPLL]. COREPLL values
Input Clock Ratio
(PLL off, csb_clk clocks core directly)
csb_clk :
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
7 : 1
8 : 1
9 : 1
core_clk : csb_clk Ratio
NOTE
PLL bypassed
2
1.5:1
1.5:1
n/a
1:1
1:1
1:1
175
200
225
250
275
300
325
350
375
25
Input Clock Frequency (MHz)
csb_clk Frequency (MHz)
(PLL off, csb_clk clocks core
33.33
233
267
300
333
367
400
VCO Divider
PLL bypassed
directly)
n/a
2
4
8
2
4
66.67
1
2
Clocking
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