HW-V5-ML555-G Xilinx Inc, HW-V5-ML555-G Datasheet - Page 56

• Manufacturer Part Number: HW-V5-ML555-G
• Description: BOARD EVAL FOR VIRTEX-5 ML555
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-ML555-G

• Contents: Board, Cables, CD
• Silicon Manufacturer: Xilinx
• Features: Parallel Connectivity, Three On-board Clock Sources
• Kit Contents: Board, Cables, CD, Power Supply
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50T-1FF1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 FPGA
• For Use With: HW-AFX-SMA-SFP - CONVERSION MODULE SMA - SFPHW-AFX-SMA-SATA - CONVERSION MODULE SMA - SATAHW-AFX-SMA-RJ45 - CONVERSION MODULE SMA - RJ45HW-AFX-SMA-HSSDC2 - CONVERSION MODULE SMA - HSSDC2HW-AFX-BERG-EPHY - DAUGHTER CARD PHY BERG-EPHY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1586; HW-V5-ML555-G

Chapter 3: Hardware Description
56
P13-A13
P13-A14
125 MHz
P1-B16
10 MHz
25 MHz
J10
J11
J12
J13
Figure 3-9: Clock Synthesis Block Diagram (Optional Customer Install Configuration)
FPGA_GCLK_30MHZ
SMA_GCLKP
SMA_GCLKN
SMA
SMA
PCIE_REFCLK
PCICLK
200 MHz
LVPECL
Driver
Clock
Synth
Clock
Synth
Clock
4.7KΩ
#1
#2
Figure 3-9
attenuator circuit. Contact your local Xilinx representative for more information on this
option.
2.5V
0
1
0
1
0
1
874003
shows an optional clock synthesis configuration, which uses an ICS874003 jitter
ICS
LVPECL_200M_P
LVPECL_200M_N
1
0
MGT_X0Y1_RCLKP
MGT_X0Y1_RCLKN
MGT_X0Y0_RCLKP
MGT_X0Y0_RCLKN
Driver
Clock
Clock
Mux
Select
(LVDS)
(LVDS)
nA0
nA1
A0
A1
Q0
Q1
0
1
www.xilinx.com
SFP_MGT_GCLKP
SFP_MGT_GCLKN
SFP_MGT_REFCLKP
SFP_MGT_REFCLKN
SATA_MGT_GCLKP
SATA_MGT_GCLKN
SATA_MGT_REFCLKP
SATA_MGT_REFCLKN
SATA_MGT_CLKSEL
PCIE250M_P
PCIE250M_N
PCIE_GCLK_P
PCIE_GCLK_N
H17
H18
H19
H20
AF4
AF3
G15
G16
H15
AL5
AL4
K17
L19
L18
J16
J17
J20
J21
J14
Y4
Y3
P4
P3
H4
H3
E4
D4
GCLK
GCLKP
GCLKN
MGT_REFCLKP
MGT_REFCLKN
GCLKP
GCLKN
GCLKP
GCLKN
MGT_REFCLKP
MGT_REFCLKN
MGT_REFCLKP
MGT_REFCLKN
MGT_REFCLKP
MGT_REFCLKN
GCLKP
GCLKN
MGT_REFCLKP
MGT_REFCLKN
GCLKP
GCLKN
MGT_REFCLKP
MGT_REFCLKN
Bank 3 I/O
GCLKP
GCLKN
GCLK
Virtex-5 FPGA ML555 Development Kit
U10 FPGA
UG201 (v1.4) March 10, 2008
GTP X0Y2
GTP X0Y1
GTP X0Y0
GTP X0Y3
GTP X0Y4
GTP X0Y5
UG201_c3_08_022608
R