HW-V5-ML555-G Xilinx Inc, HW-V5-ML555-G Datasheet - Page 71

• Manufacturer Part Number: HW-V5-ML555-G
• Description: BOARD EVAL FOR VIRTEX-5 ML555
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-ML555-G

• Contents: Board, Cables, CD
• Silicon Manufacturer: Xilinx
• Features: Parallel Connectivity, Three On-board Clock Sources
• Kit Contents: Board, Cables, CD, Power Supply
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50T-1FF1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 FPGA
• For Use With: HW-AFX-SMA-SFP - CONVERSION MODULE SMA - SFPHW-AFX-SMA-SATA - CONVERSION MODULE SMA - SATAHW-AFX-SMA-RJ45 - CONVERSION MODULE SMA - RJ45HW-AFX-SMA-HSSDC2 - CONVERSION MODULE SMA - HSSDC2HW-AFX-BERG-EPHY - DAUGHTER CARD PHY BERG-EPHY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1586; HW-V5-ML555-G

Table 3-26: FPGA Clock-Capable I/O Connectivity (Continued)
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
GPIO1_I10_N
GP1O1_I10_P
GPIO1_I11_N
GP1O1_I11_P
GPIO1_I12_N
GP1O1_I12_P
GPIO1_I13_N
GP1O1_I13_P
GPIO1_I00_N
GPIO1_I00_P
GPIO1_I01_N
GP1O1_I01_P
GPIO1_I22_N
GP1O1_I22_P
GPIO1_I23_N
GPIO1_I23_P
GPIO2_I00_N
GPIO2_I00_P
GPIO2_I01_N
GP1O2_I01_P
GPIO2_I22_N
GP1O2_I22_P
GPIO2_I23_N
GPIO2_I23_P
P0_RXC_RXCLK
P0_TXC_GTXCLK
P1_TXC_GTXCLK
P1_RXC_RXCLK
CPLD_SPARE1
CPLD_SPARE2
PCIW_EN
RTR
Signal Name
R
FPGA Pin FPGA Bank Bank V
AG23
AG12
AE23
AE22
AF23
AE12
AE13
AF13
H28
H27
H23
H12
A13
G28
G27
K22
K23
G23
K12
K13
C13
E27
E26
F28
E28
B12
B13
J12
H7
J10
K8
T8
19
12
20
1
2
www.xilinx.com
CCO
2.5
2.5
2.5
2.5
2.5
(Volts)
User-defined LVDS general-purpose I/O
interface
User-defined LVDS general-purpose I/O
interface
User-defined LVDS general-purpose I/O
interface
Ethernet PHY clocks from daughtercard
HW-AFX-BERG-EPHY
HW-AFX-BERG-EPHY
User defined
Potential dynamic reconfiguration
request or other user-defined application
using a core for PCI operation
Ethernet PHY clocks from daughtercard
Function
Clock Generation
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