HS38000EPI61H Renesas Electronics America, HS38000EPI61H Datasheet - Page 196
HS38000EPI61H
Manufacturer Part Number
HS38000EPI61H
Description
DEV EMULATOR BASE UNIT H8/38000
Manufacturer
Renesas Electronics America
Type
Microcontrollerr
Datasheet
1.HS38000EPI61H.pdf
(256 pages)
Specifications of HS38000EPI61H
Contents
E6000 Emulator and CD-ROM
For Use With/related Products
38000 Series
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 196 of 256
- Download datasheet (3Mb)
7.2 User System Interface of H8/3800 E6000 Emulator
All user system interface signals are directly connected to the MCU in the emulator with no buffering.
7.2.1
All user system interface signals are protected from over- or under-voltage by use of diode arrays except for the
AVcc and analog port signals.
Pull-up resistors are connected to the port signals except for the analog port signals.
The Vcc pins (except for the AVcc pin) at the head of the user system interface cable are connected together.
The emulator monitors the voltage level of the Vcc pins and displays the power-supply status in the [Extended
Monitor] window.
If the user system interface cable is not connected to the user system, the Vcc of the MCU is 5 V.
7.2.2
The interface circuit between the MCU in the emulator and the user system has a signal delay of about 8 ns due
to the user system interface cable and it includes pull-up resistors. Therefore, high-impedance signals will be
pulled up to the high level. When connecting the E6000 emulator to a user system, adjust the user system
hardware to compensate for propagation delays.
Default:
OSC1 and X1:
P50/WKP0/SEG1 to P57/WKP7/SEG8, P60/SEG9 to P67/SEG16, P70/SEG17 to P77/SEG24, P80/SEG25 to
P87/SEG32/CL1, PC0/COMP0 to PC3/COMP3, PB0/AN0 to PB7/AN7:
P67/SEG16, P70/SEG17 to P77/SEG24, P80/SEG25 to P87/SEG32/CL1, PC0/COMP0 to PC3/COMP3,
Figure 7.3 User System Interface Circuit for P50/WKP0/SEG1 to P57/WKP7/SEG8, P60/SEG9 to
Signal Protection
User System Interface Circuits
Evaluation
chip
Evaluation
chip
Evaluation
chip
Figure 7.2 User System Interface Circuit for OSC1 and X1
Figure 7.1 Default User System Interface Circuit
PB0/AN0 to PB7/AN7
10 k
Vcc
470 kΩ
Ω
47 Ω
47 Ω
47 Ω
Vcc
User system interface cable
User system interface cable
User system interface cable
175
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