ATF15XX-SAQ100 Atmel, ATF15XX-SAQ100 Datasheet - Page 31

• Manufacturer Part Number: ATF15XX-SAQ100
• Description: ADAPTER FOR ATF15XX-DK2 100PQFP
• Manufacturer: Atmel

Specifications of ATF15XX-SAQ100

• Accessory Type: ATF15xxDK2 Adapter
• For Use With/related Products: 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The Fitter Report (.FIT) File generated for this design is shown below.
CPLD Development/Programmer Kit User Guide
Logic Array Block
A: LC1 - LC16
B: LC17 - LC32
C: LC33 - LC48
D: LC49 - LC64
E: LC65 - LC80
F: LC81 - LC96
G: LC97 - LC112
H: LC113- LC128
Total dedicated input used:
Total I/O pins used
Total Logic cells used
Total Flip-Flop used
Total Foldback logic used
Total Nodes+FB/MCells
Total cascade used
Total input pins
Total output pins
Total Pts
Cascades
:
16/16(100%)
Logic Cells
16/16(100%)
16/16(100%)
16/16(100%)
16/16(100%)
16/16(100%)
16/16(100%)
16/16(100%)
The ATF15xx Family devices Logic Doubling features provide extra I/O connectivity and
logic reusability. Some of the Logic Doubling features available in the ATF15xx family of
CPLDs are:
n
n
n
n
n
n
n
In the LOGIC_D8.PLD example given in this tutorial, Logic Blocks B, C D, and F have
37 or more signal inputs (Fan-In's) as shown in the Universal-Interconnect-Multiplexer
assignments section of the .FIT file. The availability of wide Fan-In's to the Logic Blocks
is one of the many Logic Doubling features. This feature improves the possibility of rout-
ing all the necessary signals from the Global Bus to the Logic Blocks.
In addition, macrocells 37 and 59 of the ATF1508 are able to implement both combina-
torial outputs (LED1G and LED8D) and buried registered signals (CA0 and RST) within
the same macrocells. This is shown in the Resource Usage section of the .FIT file.
For more examples of design techniques that utilize the Logic Doubling features of the
ATF15xx Family, refer to Atmel's Logic Doubling White Paper and Reference Designs
available on the Atmel website. These examples show how to apply Logic Doubling
techniques to new product designs, to obtain the benefits of more features in a smaller
and possibly less expensive chip, or spare logic resources for future revisions and
reduce the risk of PCB re-spin.
Bury either Register or Combinatorial signal while using the other for output
Dual independent feedback allows multiple latch functions per macrocell
5 product terms per macrocell, expandable to 40 per macrocell with cascade logic,
plus 15 more with foldback logic
D/T/Latch configurable flip-flops plus transparent latches
Global and/or per macrocell Output Enable
Single level Switch Matrix
Up to 40 inputs per Logic Block
3/4
60/64
128/128 (100%)
31/128 (24%)
25/128 (19%)
153/128 (119%)
0
7
56
372
8/16(50%)
I/O Pins
8/16(50%)
8/16(50%)
8/16(50%)
6/16(37%)
6/16(37%)
8/16(50%)
8/16(50%)
(75%)
(93%)
2/16(12%)
Foldbacks
5/16(31%)
3/16(18%)
2/16(12%)
2/16(12%)
6/16(37%)
2/16(12%)
3/16(18%)
42/80(52%)
TotalPT
46/80(57%)
51/80(63%)
48/80(60%)
40/80(50%)
55/80(68%)
47/80(58%)
43/80(53%)
CPLD Design Flow Tutorial
FanIN
(19)
(38)
(38)
(38)
(32)
(38)
(25)
(34)
0
0
0
0
0
0
0
0
3300A–PLD–08/02
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