89C5121-SK1 Atmel, 89C5121-SK1 Datasheet - Page 17

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89C5121-SK1

Manufacturer Part Number
89C5121-SK1
Description
KIT SMART CARD FOR AT89C5121
Manufacturer
Atmel
Type
Smart Cardr
Datasheet

Specifications of 89C5121-SK1

Contents
Board
For Use With/related Products
AT89C5121
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C5121-SK1
T89C5121-SK1
Figure 10. Power-down Exit Waveform
SCI Control
LED Control
Low Power Mode
4164G–SCR–07/06
XTAL1
INT0
INT1
Active phase
The ports status under Power-down is the status which was valid before entering this
mode.
The INT1 interrupt is a multiplexed input (see Interrupt paragraph) with CPRES (Card
detection) and Rxd (UART Rx). So these three inputs can be used to exit from Power-
down mode. The configurations which must be set are detailed below:
Exiting from Power-down by reset redefines all the SFRs, exiting from Power-down by
external interrupt does no affect the SFRs.
Exiting from Power-down by either reset or external interrupt does not affect the internal
RAM content.
Note:
Prior to entering Power-down mode, a de-activation of the Smart Card system must be
performed.
Prior to entering Power-down mode, if the LED mode output is used, the medium pull-up
must be disconnected by setting the LEDPD bit in the PCON Register (PCON 3).
Only in Power-down mode, in order to reduce the power consumption, the user can
choose to select this low-power mode.
The activation reference is the following.
Rxd input:
CPRES input:
First select the Low-power mode by setting the LP bit in the AUXR Register (AUXR.
6)
The activation of Power-down can then be done.
RXEN (ISEL.0) must be set
EX1 (IE0.2) must be set
A low level detected during more than 100 microseconds exit from Power-
down
PRSEN (ISEL.1) must be set
EX1 (IEO.2) must be set
EA (IE0.7) must be set
In the INT1 interrupt vector, the CPLEV Bit (ISEL.7) must be inverted
and PRESIT Bit (ISEL.5) must be reset.
If idle mode is activated with Power-down mode (IDL and PD bits set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
Power-down phase
Oscillator restart phase
Active phase
A/T8xC5121
17

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