89C5121-SK1 Atmel, 89C5121-SK1 Datasheet - Page 97
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
89C5121-SK1
Manufacturer Part Number
89C5121-SK1
Description
KIT SMART CARD FOR AT89C5121
Manufacturer
Atmel
Type
Smart Cardr
Datasheet
1.89C5121-SK1.pdf
(115 pages)
Specifications of 89C5121-SK1
Contents
Board
For Use With/related Products
AT89C5121
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C5121-SK1
T89C5121-SK1
T89C5121-SK1
- Current page: 97 of 115
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WDT during Power-down
and Idle
4132C–SCR–07/06
Table 71. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset Value = XXXX X000
In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode the user does not need to service the WDT. There are 2 methods of
exiting Power-down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power-down mode. When Power-down is exited with
hardware reset, servicing the WDT should occur as it normally should whenever the
T8xC5121 is reset. Exiting Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it
is better to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
T8xC5121 while in Idle mode, the user should always set up a timer that will periodically
exit Idle, service the WDT, and re-enter Idle mode.
Number
Bit
7
-
7
6
5
4
3
2
1
0
Mnemonic Description
Bit
S2
S1
S0
6
-
-
-
-
-
-
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
S2 S1
0
0
0
0
1
1
1
1
5
-
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Selected Time-out
(2
(2
(2
(2
(2
(2
(2
(2
4
-
14
15
16
17
18
19
20
21
- 1) machine cycles, 16. 3 ms @ F
- 1) machine cycles, 32.7 ms @ F
- 1) machine cycles, 65. 5 ms @ F
- 1) machine cycles, 131 ms @ F
- 1) machine cycles, 262 ms @ F
- 1) machine cycles, 542 ms @ F
- 1) machine cycles, 1.05 ms @ F
- 1) machine cycles, 2.09 ms @ F
3
-
S2
2
A/T8xC5121
OSCA
OSCA
OSCA
OSCA
OSCA
OSCA
OSCA
OSCA
S1
1
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
S0
0
97
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