AD8320-EB Analog Devices Inc, AD8320-EB Datasheet - Page 10

• Manufacturer Part Number: AD8320-EB
• Description: BOARD EVAL FOR AD8320
• Manufacturer: Analog Devices Inc

Specifications of AD8320-EB

• Rohs Status: RoHS non-compliant
• Channels Per Ic: 1 - Single
• Amplifier Type: Variable Gain
• Output Type: Single-Ended
• -3db Bandwidth: 150MHz
• Operating Temperature: -40°C ~ 85°C
• Current - Supply (main Ic): 97mA
• Voltage - Supply, Single/dual (±): 5 V ~ 12 V
• Board Type: Fully Populated
• Utilized Ic / Part: AD8320
• Lead Free Status / Rohs Status: Not Compliant

AD8320
The power amplifier has two basic modes of operation; forward
or power-up mode and reverse or power-down mode. In the
power-up mode (PD = 1), the power amplifier stage is enabled
and the differential output core signal is amplified by 20 dB.
With a core attenuation range of 0 dB to –36 dB and 6 dB of
input gain, the overall AD8320 gain range is 26 dB to –10 dB.
In this mode, the single-ended output signal maintains a dc
level of VCC/2. This dc output level provides for optimum large
signal linearity and allows for dc coupling the output if neces-
sary. The output stage is unique in that it maintains a dynamic
output impedance of 75 . This allows for a direct 75
connection and results in 6 dB of added load power versus using
a series 75
tional low output impedance amplifiers. The power amplifier
will also drive lower or higher output loads, although the device’s
gain (not gain range) will change accordingly (see Applications
section).
In the power-down mode (PD = 0), the power amplifier is turned
off and a “reverse” amplifier (the inner triangle in Figure 42) is
enabled. During this 1 to 0 transition, the output power amplifier’s
input stage is also disabled, resulting in no forward output signal
(S21 is 0), although the attenuator core and input amplifier/
buffer signals are not affected (S11
reverse amplifier is to maintain 75
port (VOUT) during power-down. This is required to minimize
line reflections (S22
any forward mode device sharing the same bus (i.e., in a multi-
plexed configuration). (See Applications section.) In the time
domain, as PD switches states, a transitional glitch and pedestal
offset results. (See Figures 31 and 43.) The powered down
supply current drops to 32 mA versus 97 mA (V
power-up mode.
Generally, using the power-down low input (PD) for switching
allows for multiple devices to be multiplexed via splitters (N-1
off, 1 on) and reduces overall total power consumption as re-
quired for cable data applications. For cable telephony, the
power-down current generally needs to be much lower during
back-termination resistor as required with tradi-
0) and ensures proper filter operation for
ANALOG
OUTPUT
SDATA
DATEN
CLK
PD
and VCC/2 at the output
0). The function of the
SIGNAL AMPLITUDE (p-p)
T
ES
VALID DATA WORD G1
8 CLOCK CYCLES
CC
T
Figure 43. Serial Interface Timing
DS
MSB. . . .LSB
= 12 V) in
T
C
cable
T
T
WH
EH
GAIN TRANSFER (G1)
T
GS
–10–
what is referred to as sleep and standby modes, and VCC supply
switching via PFETS or equivalent, as described in the applica-
tions section, would be required.
APPLICATIONS
The AD8320 is primarily intended to be used as the return path
(also called upstream path) line driver in cable modem and
cable telephony applications. Data to be transmitted is modu-
lated in either QPSK or QAM format. This is done either in
DSP or by a dedicated QPSK/QAM modulator such as the
AD9853.
The amplifier receives its input signal either from the dedicated
QPSK/QAM modulator or from a DAC. In both cases, the
signal must be low-pass filtered before being applied to the line
driving amplifier.
The amplifier drives the line through a diplexer. The insertion
loss of a diplexer is typically –3 dB. As a result, the line driver
must deliver a power level roughly 3 dB greater than required by
the applicable cable modem standard so that diplexer losses are
canceled out.
Because the distance to the central office varies from subscriber
to subscriber, signals from different subscribers will be attenu-
ated by differing amounts. As a result, the line driver is required
to vary its gain so that all signals arriving at the central office
have the same amplitude.
Figure 44. Block Diagram of Cable Modem’s Upstream
Driver Section
AD9853
T
OFF
VALID DATA WORD G2
PEDESTAL
7TH ORDER
LOW PASS
ELLIPTIC
FILTER
GAIN TRANSFER (G2)
TO MODEM
CIRCUITRY
RECEIVE
AD8320
T
ON
DIPLEXER
SUBSCRIBER
CENTRAL
OFFICE
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