AD8320-EB Analog Devices Inc, AD8320-EB Datasheet - Page 9

• Manufacturer Part Number: AD8320-EB
• Description: BOARD EVAL FOR AD8320
• Manufacturer: Analog Devices Inc

Specifications of AD8320-EB

• Rohs Status: RoHS non-compliant
• Channels Per Ic: 1 - Single
• Amplifier Type: Variable Gain
• Output Type: Single-Ended
• -3db Bandwidth: 150MHz
• Operating Temperature: -40°C ~ 85°C
• Current - Supply (main Ic): 97mA
• Voltage - Supply, Single/dual (±): 5 V ~ 12 V
• Board Type: Fully Populated
• Utilized Ic / Part: AD8320
• Lead Free Status / Rohs Status: Not Compliant

OPERATIONAL DESCRIPTION
The AD8320 is a digitally controlled variable gain power ampli-
fier that is optimized for driving 75
bipolar device on single silicon, it incorporates all the analog
features necessary to accommodate reverse path (upstream) high
speed (5 MHz to 65 MHz) cable data modem and cable tele-
phony requirements. The AD8320 has an overall gain range of
36 dB (–10 dB to 26 dB) and is capable of greater than 100 MHz
of operation at output signal levels exceeding 18 dBm. Overall,
when considering the device’s wide gain range, low distortion,
wide bandwidth and variable load drive, the device can be used
in many variable gain block applications.
The digitally programmable gain is controlled by the three wire
“SPI” compatible inputs. These inputs are called SDATA
(serial data input port), DATEN (data enable low input port)
and CLK (clock input port). See Pin Function Descriptions and
Functional Block diagram. The AD8320 is programmed by an
8-bit “attenuator” word. These eight bits determine the 256
programmable gain settings. See attenuator core description
below. The gain is linear in V/V/LSB and can be described by
the following equation:
where code is the decimal equivalent of the 8-bit word. For ex-
ample, if all 8 bits are at a logic “1,” the decimal equivalent is
255 and A
is 0.077 V/V/LSB, with an offset of 0.316 V/V (–10.0 dB). Fig-
ure 40 shows the linear gain versus decimal code and Figure 41
shows the gain in dB versus decimal code. Note the nonlin-
earity that results when viewed in dB versus code. The dB step
size increases as the attenuation increases (i.e., gain decreases)
and reaches a maximum step size of approximately 1.9 dB (gain
change between 01 and 00 decimal).
The AD8320 is composed of three analog functions in the power-
up or forward mode (Figure 42). The input inverter/buffer
amplifier provides single-ended to differential output conver-
sion. The output signals are nominally 180 degrees out of phase
and equal in amplitude with a differential voltage gain of 2 (6 dB).
Maintaining close to 180 degrees and equal amplitude is re-
quired for proper gain accuracy of the attenuator core over the
specified operating frequency. The input buffer/inverter also
provides equal dc voltages to the core inputs via the internal
reference. This is required to ensure proper core linearity over
the full specified power supply range (5 V to 12 V).
REV. 0
22
20
18
16
14
12
10
–2
8
6
4
0
2
0
V
Figure 40. Linear Gain vs. Gain Control
A
A
equals 19.95 V/V or 26 dB. The gain scaling factor
V
= 0.316 + 0.077
V
32
= 0.316 + 0.077
64
GAIN – Code – Decimal
CODE
96
POWER-UP
128
Code (R
POWER-DOWN
cable. A multifunctional
160
L
192
= 75 )
224
256
–9–
The attenuator core can be viewed as eight binarily weighted
(differential in–differential out) transconductance (gm) stages
with the “in phase” current outputs of all eight stages connected
in parallel to their respective differential load resistors (not
shown). The core differential output signals are also 180 degrees
out of phase and equal in amplitude. The input stages are like-
wise parallel, connected to the inverting input amplifier and
buffer outputs as shown. Nine bits plus of accuracy is achieved
for all gain settings over the specified frequency, supply voltage
and temperature range. The actual total core GM RL attenua-
tion is determined by which combination of binarily weighted
gm stages are selected by the data latch. With 8 bits, 256 levels
of attenuation can be programmed. This results in a 36 dB
attenuation range (0 dB to –36 dB). See gain equation above.
To update the AD8320 gain, the following digital load sequence
is required. The attenuation setting is determined by the 8-bit
word in the data latch. This 8-bit word is serially loaded (MSB
first) into the shift register at each rising edge of the clock. See
Figure 43. During this data load time (T), DATEN is low and
the data latch is latched holding the previous (T – 1) data word
keeping the attenuation level unchanged. After eight clock
cycles the new data word is fully loaded and DATEN is
switched high. This enables the data latch (becomes transpar-
ent) and the loaded register data is passed to the attenuator with
the updated gain value. Also at this DATEN transition, the
internal clock is disabled, thus inhibiting new serial input data.
VREF
VIN
–16
DATEN CLK
32
24
16
–8
8
0
0
Figure 41. Log Gain vs. Gain Control
REFERENCE
Figure 42. Functional Block Diagram
INV.
BUF.
32
VCC
64
DATA SHIFT REGISTER
A
ATTENUATOR CORE
GAIN – Code – Decimal
V
GND
AD8320
= 20
96
DATA LATCH
LOG
128
10
(0.316 + 0.077
160
SDATA
192
POWER–
AD8320
SWITCH
INTER.
DOWN
CODE)
224
PWR AMP
REVERSE
AMP
256
VOUT
PD