EVAL-AD1953EB Analog Devices Inc, EVAL-AD1953EB Datasheet - Page 3

• Manufacturer Part Number: EVAL-AD1953EB
• Description: BOARD EVAL FOR AD1953
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1953EB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

the column entries are the signal sources and the headings are the
signal destinations for a given switch position.
Note: Switch position F is not used.
SW2
Pos. MUX 0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
SW2
Pos.
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
*MCLK input signals to the CS8404 are divided by two in the PLD because
Rotary switch SW3 determines which serial interface format is
selected. Table IV shows the different modes.
Note: Switch positions 6–F are not used.
REV. 0
this part runs on 128 f
Table III. SW2 Settings—CS8404A Signal Sources
8414
Ext. port 0
Ext. port 0
Ext. port 0
8414
Ext. port 0
Ext. port 0
Ext. port 0
8414
Ext. port 0
Ext. port 0
ASDATA1 ASDATA1
ASDATA2 ASDATA2
ASDATA1 ASDATA1
ASDATA2 ASDATA2
8404
SDI
DCSOUT
DCSOUT
DCSOUT
DCSOUT
SDATAOUT MUX OUT
SDATAOUT MUX OUT
SDATAOUT MUX OUT
SDATAOUT MUX OUT
DCSOUT
DCSOUT
DCSOUT
DCSOUT
DCSOUT
SDATAOUT MUX OUT
SDATAOUT MUX OUT
Table II. SW2 Settings—Signal Sources
SW3 Position
0
1
2
3
4
5
S
, while the rest of the board runs on a 256 f
Table IV. SW3 Settings
MUX 1
Ext. port 1
8414
Ext. port 1
Ext. port 1
Ext. port 1
8414
Ext. port 1
Ext. port 1
Ext. port 1
8414
Ext. port 1
8404
LRCLK/BCLK MCLK (128 f
8414
8414
8414
MUX OUT
MUX OUT
MUX OUT
MUX OUT
MUX OUT
MUX OUT
Serial Data Format
I
Right Justified — 24-bit
DSP
Left Justified
Right Justified — 20-bit
Right Justified — 16-bit
2
S
MUX 2
Ext. port 2
Ext. port 2
8414
Ext. port 2
Ext. port 2
Ext. port 2
8414
Ext. port 2
Ext. port 2
Ext. port 2
8414
ASDATA1
ASDATA2
ASDATA1
ASDATA2
8404
8414 (* 1/2)
8414 (* 1/2)
8414 (* 1/2)
MCLKOUT (* 1/2)
8414 (* 1/2)
8414 (* 1/2)
8414 (* 1/2)
8414 (* 1/2)
MCLKOUT (* 1/2)
MCLKOUT (* 1/2)
MCLKOUT (* 1/2)
Ext. CODEC (* 1/2)
Ext. CODEC (* 1/2)
Ext. CODEC (* 1/2)
Ext. CODEC (* 1/2)
AUXDATA
Ext. port 0
Ext. port 1
Ext. port 2
8414
Ext. port 0
Ext. port 1
Ext. port 2
8414
Ext. port 0
Ext. port 1
Ext. port 2
ASDATA2
ASDATA1
ASDATA2
ASDATA1
S
MCLK.
S
)*
–3–
Switch S2 enables the AD1953 mute function.
Push-button switch SW4 and switches S4 and S5 are not currently
functional but will be used in future evaluation board revisions.
Jumper LK2 selects between an external supply (Position A) or
a 5 V input (Position B) to the AD1953’s ODVDD pin. ODVDD
is the supply for the digital output pins. Using an external supply
at 3 V allows the outputs to be 3.3 V compatible. The switch
should be left in the 5 V position if no external power supply is
connected to the EXT side of the jumper.
Jumper LK9, LK10, and LK11 select between internal and exter-
nal MCLK inputs to the MCLK MUX for MCLK0, MCLK1, and
MCLK2, respectively. For LK9, Position A selects the
MCLK0_INTF from External Data Interface 0 (J14), Position B
selects the MCLK from the codec interface header (J17), and
Position C selects the recovered DIR_MCLK from the S/PDIF
receiver (U2). For LK10 and LK11, in the left Position (A), the
DIR_MCLK signal from U2 is selected. Position B selects the
MCLKx_INTF signal from external data header J15 and J16.
Jumpers LK5 and LK6 connect the reference voltage to the
VREF_IN pin. If LK5 is on, then the voltage will come from
AVDD. With LK6 on, the reference voltage will be taken from
the external reference Test Point 1 (TP1).
INDICATOR DISPLAY LEDS
Five LED indicators are provided for status indication.
•
•
•
•
INTEGRATED CIRCUIT FUNCTIONS
There are 16 active devices on the AD1953 evaluation board.
Following is a brief description of the function of each part.
•
•
•
•
Display LED D1, VERF, indicates that the S/PDIF digital
interface receiver has detected an error condition in the
received signal. When not illuminated, this LED is a good
indicator that there is a signal present on the S/PDIF input.
Display LED D2, EMP, indicates that the incoming signal
has had pre-emphasis added.
Display LED D3, ZERO, is provided to show that the
AD1953 is detecting a zero input in one of the two input
channels.
Display LEDs D6 and D11, DVDD and AVDD, show the
presence of 5 V dc on the digital and analog 5 V power
supplies, respectively.
U1 (TORX173) is the Toshiba digital audio optical receiver.
It accepts the visible red S/PDIF modulated signal and
converts it to a standard TTL digital signal suitable for
input to the digital audio receiver (U2).
U2 (CS8414-CS) receives the serial S/PDIF digital audio
encoded signal and decodes the audio information. The
CS8414 decodes four digital signals from the serial input
stream: the serial data SDATA, the master clock MCLK,
the left/right frame clock LRCLK, and the serial bit clock
BCLK at 64 Fs. The output interface mode of U2 must be
compatible with the input to the AD1953 (U7). This mode
is selected at the same time for both U2 and U7 via switch SW3.
U3 (74HC04) is a quad input logic inverter that provides
miscellaneous buffering and interface functions.
U4 (CS8404A-CS) is the S/PDIF transmitter that takes in
the serial data SDATA, master clock MCLK, the left/right
EVAL-AD1953EB