EVAL-ADUC7024QS Analog Devices Inc, EVAL-ADUC7024QS Datasheet - Page 3

• Manufacturer Part Number: EVAL-ADUC7024QS
• Description: KIT DEV FOR ADUC7024/7025
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: ARM7 Processor, Microcontrollerr

Specifications of EVAL-ADUC7024QS

• Mfg Application Notes: ADUC7024 Eval Board/Dev System, AN-719
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• For Use With/related Products: ADuC7024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: EVAL-ADUC7024QS-U2

4. On-Chip Loader’s Write/Verify Commands [er020]:
Background:
Issue:
Workaround:
Related Issues:
5. I
Background:
Issue:
Workaround:
Related Issues:
2
C Slave Not Releasing the Bus [er021]:
The on-chip factory firmware residing in 2 kB of Flash/EE memory allows the downloading of user code from Intel HEX
files to user space in Flash/EE memory via a serial port (either UART or I
downloading, it also allows verification that the Flash/EE memory has been programmed properly.
Both the write command and verify command, as described in
• If the address of the first byte of the data packet to be programmed is odd, the data at the previous address
• If the address of the last byte of the data packet to be programmed is even, this byte is not written into Flash/EE
ARMWSD Version 6.8 and higher ensures that the data starts and terminates on half word boundaries. Dummy bytes
(0xFF) are added to data packets that do not start/stop on half word boundaries.
Users employing their own software for downloading should also take this precaution.
None.
During a read from the master to the slave, if the slave’s FIFO is empty, the slave generates a NACK in response to the
master’s request. Then it releases the bus, allowing the master to generate a STOP condition.
Following generation of a no acknowledge, the ADuC7019/ADuC702x may not release the bus due to the generation
of a FIFO transmit empty interrupt.
Following the generation of a transmit FIFO empty interrupt, the bus can be released by any of the following:
• Placing valid data in the transmit FIFO
• Placing dummy data in the transmit FIFO, followed by a transmit FIFO flush
• Resetting the slave interface by disabling/enabling the slave
None.
becomes corrupted.
memory.
Rev. B | Page 3 of 4
AN-724
2
and AN-806, cause issues with odd addresses:
C, depending on the model). After
ADuC7019/ADuC702x