EVAL-AD7686CB Analog Devices Inc, EVAL-AD7686CB Datasheet - Page 18

• Manufacturer Part Number: EVAL-AD7686CB
• Description: BOARD EVALUATION FOR AD7686
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7686CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 15mW @ 500kSPS, 5 V
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7686
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7686
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is generally used when a single AD7686 is connected
to an SPI-compatible digital host having an interrupt input. The
connection diagram is shown in Figure 35, and the correspond-
ing timing is provided in Figure 36.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion, irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers. However,
CNV must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data reading controlled by the
digital host. The AD7686 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK edges.
ACQUISITION
SDI = 1
CNV
SCK
SDO
CONVERSION
Figure 36. CS Mode 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
t
CONV
t
CNVH
1
Rev. B | Page 18 of 28
t
t
HSDO
DSDO
D15
2
t
CYC
ACQUISITION
D14
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
17th SCK falling edge or when CNV goes high, whichever
occurs first, SDO returns to high impedance.
If multiple AD7686s are selected at the same time, the SDO
output pin handles this connection without damage or induced
latch-up. Meanwhile, it is recommended to keep this connection as
short as possible to limit extra power dissipation.
t
3
ACQ
t
VIO
SCKL
t
SCKH
15
SDI
Figure 35. CS Mode 3-Wire with Busy Indicator
AD7686
t
SCK
CNV
SCK
Connection Diagram (SDI High)
16
D1
SDO
17
D0
VIO
47kΩ
t
DIS
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST