EVAL-AD7693CB Analog Devices Inc, EVAL-AD7693CB Datasheet - Page 17

• Manufacturer Part Number: EVAL-AD7693CB
• Description: BOARD EVAL FOR AD7693 ADC
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7693CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 18mW @ 500kSPS
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7693
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 34, and the corresponding timing is given in
Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This could be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
SDI = 1
ACQUISITION
CNV
SCK
SDO
t
CNVH
Figure 35. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
CONVERSION
t
CONV
VIO
Figure 34. CS Mode, 3-Wire Without Busy Indicator
SDI
t
AD7693
EN
CNV
SCK
Connection Diagram (SDI High)
D15
1
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t
SDO
HSDO
D14
2
t
CYC
ACQUISITION
D13
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator. When the
conversion is complete, the AD7693 enters the acquisition
phase and powers down. When CNV goes low, the MSB is
output onto SDO. The remaining data bits are clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16
occurs first), SDO returns to high impedance.
t
3
ACQ
t
DSDO
th
CLK
CONVERT
DATA IN
DIGITAL HOST
SCK falling edge or when CNV goes high (whichever
t
SCKL
t
SCKH
14
t
SCK
15
D1
16
D0
t
DIS
AD7693