Z86E4000ZDV Zilog, Z86E4000ZDV Datasheet - Page 41

• Manufacturer Part Number: Z86E4000ZDV
• Description: 44 PIN PLCC ADAPTER
• Manufacturer: Zilog

Specifications of Z86E4000ZDV

• Convert From (adapter End): 40-Pin DIP ZIF Socket
• Convert To (adapter End): 44-PLCC Plug
• For Use With/related Products: Zilog Emulators/Programmers
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-2015

Zilog
Comparator Output Port 3 (D0). Bit 0 controls the com-
parator output in Port 3. A “1” in this location brings the
comparator outputs to P34 and P37, and a “0” releases the
Port to its standard I/O configuration. The default value
is 0.
Port 1 Open-Drain (D1). Port 1 can be configured as an
open-drain by resetting this bit (D1=0) or configured as
push-pull active by setting this bit (D1=1). The default val-
ue is 1.
Port 0 Open-Drain (D2). Port 0 can be configured as an
open-drain by resetting this bit (D2=0) or configured as
push-pull active by setting this bit (D2=1). The default val-
ue is 1.
Low EMI Port 0 (D3). Port 0 can be configured as a Low
EMI Port by resetting this bit (D3=0) or configured as a
Standard Port by setting this bit (D3=1). The default value
is 1.
Low EMI Port 1 (D4). Port 1 can be configured as a Low
EMI Port by resetting this bit (D4=0) or configured as a
Standard Port by setting this bit (D4=1). The default value
is 1. Note: The emulator does not support Port 1 low EMI
mode and must be set D4 = 1.
Low EMI Port 2 (D5). Port 2 can be configured as a Low
EMI Port by resetting this bit (D5=0) or configured as a
Standard Port by setting this bit (D5=1). The default value
is 1.
DS97Z8X0502
P R E L I M I N A R Y
Low EMI Port 3 (D6). Port 3 can be configured as a Low
EMI Port by resetting this bit (D6=0) or configured as a
Standard Port by setting this bit (D6=1). The default value
is 1.
Low EMI OSC (D7). This bit of the PCON Register con-
trols the low EMI noise oscillator. A “1” in this location con-
figures the oscillator with standard drive. While a “0” con-
figures the oscillator with low noise drive, however, it does
not affect the relationship of SCLK and XTAL. The low EMI
mode will reduce the drive of the oscillator (OSC). The de-
fault value is 1. Note: 4 MHz is the maximum external
clock frequency when running in the low EMI oscillator
mode.
Stop-Mode Recovery Register (SMR). This register
selects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 31). All bits are Write Only
except bit 7 which is a Read Only. Bit 7 is a flag bit that is
hardware set on the condition of STOP Recovery and
reset by a power-on cycle. Bit 6 controls whether a low or
high level is required from the recovery source. Bit 5
controls the reset delay after recovery. Bits 2, 3, and 4 of
the SMR register specify the Stop-Mode Recovery Source.
The SMR is located in Bank F of the Expanded Register
Group at address 0BH.
Z8 4K OTP Microcontroller
Z86E30/E31/E40
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