M68ICS08RK2 Freescale Semiconductor, M68ICS08RK2 Datasheet - Page 62

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M68ICS08RK2

Manufacturer Part Number
M68ICS08RK2
Description
SIM PROGRAM FOR 68HC908RK2
Manufacturer
Freescale Semiconductor
Type
Simulator/Programmerr
Datasheet

Specifications of M68ICS08RK2

Contents
Programmer, Power Supply, Assembler/Simulator/Debugger, Cable, Software and Documentation
For Use With/related Products
68HC908RK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Technical Reference and Troubleshooting
User’s Manual
62
7. Make sure that the MCU can enter and remain in monitor mode. For this
frequency required for a 9600-baud communications rate. If the clock
signal is not present, check to see that a jumper is installed on Wr. This
selects the RKICS as the source of the OSC1 signal.
to happen, the following conditions must occur:
Technical Reference and Troubleshooting
b. At the rising edge of RST, PTA0, PTB0, PTB2, and PTB3 must be
a. At the rising edge of RST, IRQ must be at V
c. Either RST or IRQ must remain at +7.5 Vdc to hold the MCU in
a dual-trace oscilloscope, trigger channel 1 on the rising edge of
RST (XU1 pin 13, XU2 pin 13, or XU3 pin 26) and read the
IRQ pin (XU1 pin 12, XU2 pin 12, or XU3 pin 25) with Channel 2.
Start the ICS08RKZ software as described in 2.4 Installing the
Hardware and verify that the IRQ signal is approximately
+7.5 Vdc when RST rises. If IRQ is not at +7.5 Vdc, there may be
a problem with the RKICS board’s IRQ circuit. Check R1, R15,
R16, R27, U10, U12, and U13 for the proper signals to keep IRQ at
+7.5 Vdc during the period where RST is low.
held at logic values 1, 1, 0, and 0, respectively. The logic levels are
+3.3-volt CMOS logic levels (with the factory default setting of
+3.3 V on jumper J4). Using a dual-trace oscilloscope, trigger
channel 1 on the rising edge of RST (XU1 pin 13, XU2 pin 13, or
XU3 pin 26) and read the corresponding MCU pin with channel 2.
PTA0 (XU1 pin 1, XU2 pin 1, or XU3 pin 2) is the serial data pin
to and from the host PC and should be around +3.3 Vdc at the rising
edge of RST. PTB0 (XU1 pin 2, XU2 pin 2, or XU3 pin 39), PTB2
(XU1 pin 4, XU2 pin 4, or XU3 pin 5), and PTB3 (XU1 pin 7, XU2
pin 7, or XU3 pin 20) are controlled by analog switch U2 and
should be approximately +3.3 V, 0 V, and 0 V, respectively, at the
rising edge of RST. Port pins PTB0, PTB2, and PTB3 are
connected to the target connector pins after the rising edge of RST
and are then available for target system connections. The MCU’s
PTA0 pin is never connected to the target pins, as it is used for host
communication.
monitor mode. The RKICS board has an interrupt lock out feature
to keep IRQ at 7.5 Vdc when the RST or RST-IN signal is asserted
M68ICS08RK In-Circuit Simulator — Rev. 1
TST
(+7.5 Vdc). Using
MOTOROLA

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