MPC566EVB Freescale Semiconductor, MPC566EVB Datasheet - Page 7

• Manufacturer Part Number: MPC566EVB
• Description: KIT EVALUATION FOR MPC565/566
• Manufacturer: Freescale Semiconductor

Specifications of MPC566EVB

• Processor To Be Evaluated: MPC56x
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

1.2.14 Queued Serial Multi-Channel Modules (QSMCM)
1.2.15 Electrical Specifications and Packaging
MOTOROLA
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Two queued serial modules with one queued-SPI and two SCI each (QSMCM_A, QSMCM_B)
— QSMCM_A matches full MPC555 QSMCM functionality
— QSMCM_B has pins muxed with DLCMD2 module
Queued-SPI
— Provides full-duplex communication port for peripheral expansion or interprocessor
— Up to 32 preprogrammed transfers, reducing overhead
— Synchronous serial interface with baud rate of up to system clock / 4
— Four programmable peripheral-select pins support up to 16 devices
— Special wrap-around mode allows continuous sampling of a serial peripheral for efficient
SCI
— UART mode provides NRZ format and half- or full-duplex interface
— 16 register receive buffer and 16 register transmit buffer on one SCI
— Advanced error detection, and optional parity generation and detection
— Word length programmable as 8 or 9 bits
— Separate transmitter and receiver enable bits, and double buffering of data
— Wake-up functions allow the CPU to run uninterrupted until either a true idle line is detected,
40 MHz operation (56 MHz operation is optional for the MPC566)
-40 ° C – 125 ° C ambient temperature, -40 ° C – 85 ° C for suffix C device, -55 ° C– 125 ° C for suffix A
devices
2.6 V ± 0.1 V external bus
— External bus is compatible with external memory devices operating from 2.5 V to 3.4 V.
— Extended voltage range (2.7 – 3.4 V) degrades data drive timing by 1.1 ns on date writes.
2.6 ± 0.1 V internal logic
5-V I/O (5.0 ± 0.25 V)
Available in package or bumped die
Plastic ball grid array (PBGA) packaging
1.0 mm ball pitch
– Two pins are muxed with DLCMD2 (J1850) transmit and receive pins
– QSMCM B vs J1850 mux control provided by QPAPCS3 bit in QSMCM pin assignment
communication
interfacing to serial analog-to-digital (A/D) converters
or a new address byte is received
– 388 ball PBGA
– 27 mm x 27 mm body size
(B_PCS3_J1850_TX and B_RXD2_J1850_RX)
register (PQSPAR)
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC565/MPC566 Product Brief
Go to: www.freescale.com
Detailed Feature List
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