HS2556EPI61H Renesas Electronics America, HS2556EPI61H Datasheet - Page 213

• Manufacturer Part Number: HS2556EPI61H
• Description: EMULATOR BASE H8SX/2556
• Manufacturer: Renesas Electronics America

Specifications of HS2556EPI61H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.1.8
The following tables show examples of signals to indicate the bus states and areas that can be acquired by the
emulator.
Table 8.7
Table 8.8
Note: The signals to indicate bus states and areas are used to set the [Bus/Area] condition of the event point.
8.1.9
This emulator incorporates the bus monitoring circuit as the standard, which thus allows a use of the monitoring
function to update the content of memory without affecting the realtime operation.
8.1.10
This emulator incorporates the bus monitoring circuit as the standard, which thus allows a use of trigger points
that can be set on the [Trigger] sheet in the [Event] window.
Bus State
CPU Prefetch
CPU Data
Refresh
DMAC
DTC
Other
Area
On-chip ROM
On-chip RAM
On-chip I/O 16bit
On-chip I/O 8bit
External 16bit
External 8bit
DTC RAM
They can also be acquired as the trace information. The bus state signals are also used to set the
condition not to acquire the trace ([Suppress] option) and in the Access Count Of Specified Range
Measurement mode for measuring the hardware performance ([Access Type] option).
Signals to Indicate Bus States and Areas
Monitoring Function
Trigger Points
Bus State Signals Acquired by the Emulator
Area Signals Acquired by the Emulator
Trace Display (Status)
PROG
DATA
REFRESH
DMAC
DTC
OTHER
Trace Display (Area)
ROM
RAM
I/O-16
I/O-8
EXT-16
EXT-8
RAM/DTC
Description
CPU prefetch cycles
CPU data access cycles
Refresh cycles
DMAC cycles
DTC cycles
Others
Description
ROM
RAM
16-bit I/O
8-bit I/O
16-bit EXT (external)
8-bit EXT (external)
DTCRAM
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