HS7705KCI02H Renesas Electronics America, HS7705KCI02H Datasheet - Page 226

• Manufacturer Part Number: HS7705KCI02H
• Description: ON CHIP DEBUG EMULATOR W/TRACE
• Manufacturer: Renesas Electronics America

Specifications of HS7705KCI02H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.5.2
In addition to BREAKPOINT functions, the emulator has Break Condition functions. In the HDI,
three types of conditions can be set under Break Condition 1, 2, 3. Table 6.5 lists these conditions
of Break Condition.
Table 6.5 Types of Break Conditions
Note: When cache fill cycle is acquired, the I-bus must be selected.
200
Break Condition Type
Address bus condition (Address)
Data bus condition (Data)
Bus state condition
(Bus State)
Internal I/O break condition
LDTLB instruction break condition
Count
Break Condition Functions
Description
Breaks when the SH7705 address bus value or the program
counter value matches the specified value.
Breaks when the SH7705 data bus value matches the
specified value. Byte, word, or longword can be specified as
the access data size.
There are two bus state condition settings:
Read/Write condition: Breaks when the SH7705 RD or
RDWR signal level matches the specified condition.
Bus state condition: Breaks when the operating state in an
SH7705 bus cycle matches the specified condition.
Types of buses that can be specified are listed below.
Breaks when the SH7705 accesses the internal I/O.
Breaks when the SH7705 executes the LDTLB instruction.
Breaks when the conditions set are satisfied the specified
number of times.
L-bus (CPU-ALL): Indicates an instruction fetch and
data access, including a hit to the cache memory.
L-bus (CPU-Data): Indicates a data access by the CPU,
including a hit to the cache memory.
I-bus (CPU.DMA): Indicates a CPU cycle when the
cache memory is not hit, and a data access by the
DMA.