MPC5534EVBGHS Freescale Semiconductor, MPC5534EVBGHS Datasheet - Page 10

• Manufacturer Part Number: MPC5534EVBGHS
• Description: KIT EVAL GREEN HILLS SOFTWARE
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC5534EVBGHS

• Contents: Eval Board and Demo Software
• Processor To Be Evaluated: MPC55xx
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• Core Architecture: Power
• For Use With/related Products: MPC5534
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
3.7
Power sequencing between the 1.5 V power supply and V
if using an external 1.5 V power supply with V
V
controller is not used. Refer to
Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).”
Power sequencing requires that V
before the POR signal negates. Refer to
VDD33.”
Although power sequencing is not required between V
not lead V
within specification. Higher spikes in the emitter current of the pass transistor occur if V
V
supply circuitry and the amount of board level capacitance.
Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase
of the current consumed by V
consumed can drop V
1.5 V POR asserts and stops the system clock, causing the voltage on V
negates again. All oscillations stop when V
1
2
3
4
5
6
7
8
9
10
10
Spec
RC33
DDSYN
The internal POR signals are V
RESET must remain asserted until the power supplies are within the operating conditions as specified in
Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the
internal POR asserts.
V
Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.
It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.
At peak current for device.
Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal
traces/routing from the V
transistor to the V
(less than 1 ). V
bulk capacitor (greater than 4 F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of
eight 0.01 F, two 0.1 F, and one 1 F capacitors around the package on the V
I
Refer to
Values are based on I
BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (I
10
VRCCTL
9
IL_S
(Table
must be powered up within the specified operating range, even if the on-chip voltage regulator
Absolute value of slew rate on power supply pins
Required gain at Tj:
I
6, 7, 8, 9
DD
by more than these amounts. The value of that higher spike in current depends on the board power
is measured at the following conditions: V
Table 1
Power-Up/Down Sequencing
DDSYN

I
9, Spec15) is guaranteed to scale with V
VRCCTL
for the maximum operating frequency.
RCCTL
DD
by more than 600 mV or lag by more than 100 mV for the V
(@ f
package signals must have a maximum of 100 nH inductance and minimal resistance
DD
must have a nominal 1 F phase compensation capacitor to ground. V
DD
RCCTL
sys
from high-use applications as explained in the I
Table 6. V
low enough to assert the 1.5 V POR again. Oscillations are possible when the
= f
MAX
package signal to the base of the external pass transistor and between the emitter of the pass
POR15
RC33
)
Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),”
Characteristic
, V
MPC5534 Microcontroller Data Sheet, Rev. 5
RC
DD33
. If V
POR33
and POR Electrical Specifications (continued)
must reach a certain voltage where the values are read as ones
– 40
25
150
RC33
, and V
Section 3.7.1, “Input Value of Pins During POR Dependent on
o
o
C
o
RC33
DD
C
C
lags V
POR5
DDEH6
= 1.35 V, V
RC33
is powered sufficiently.
. On power up, assert RESET before the internal POR negates.
DDSYN
down to V
tied to ground (GND). To avoid power-sequencing,
RC33
RC33
DDSYN
by more than 100 mV, the increase in current
= 3.1 V, V
and V
POR5
DD
.
or the RESET power supplies is required
Electrical Specification.
DDSYN
VRCCTL
DD
supply signals.
DD
Symbol
BETA
during power up, V
= 2.2 V.
—
to rise until the 1.5 V POR
10
RC
DD
stage turn-on to operate
must have a 20 F (nominal)
Freescale Semiconductor
Min.
35
40
50
—
RC33
Table 9
and
DD
leads or lags
Max.

500
RC33
50
—
—
DC Electrical
I
VRCCTL
must
Units
V/ms
—
—
—
).