MPC5534EVBGHS Freescale Semiconductor, MPC5534EVBGHS Datasheet - Page 58

• Manufacturer Part Number: MPC5534EVBGHS
• Description: KIT EVAL GREEN HILLS SOFTWARE
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC5534EVBGHS

• Contents: Eval Board and Demo Software
• Processor To Be Evaluated: MPC55xx
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• Core Architecture: Power
• For Use With/related Products: MPC5534
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision History for the MPC5534 Data Sheet
58
Table
Figure
Table
Table
Figure
Figure
Location
25, eMIOS Timing:
26, DSPI Timing:
27, EQADC SSI Timing Characteristics:
17, eMIOS Timing: Added figure.
28, MPC5534 208 Package and
30, MPC5534 208 Package Dimensions and
Deleted the version number and date.
• Deleted (MTS) from the heading, table, and footnotes.
• Footnote 1: Changed ‘V
• Footnote 1: Deleted ‘F
• Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
• Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum
• Spec1:SCK Cycle Time: changes to values: 40 MHz, min. = 48.8 ns, max = 5.8 ms; 66 MHz, min. = 28.4 ns,
• Spec 2: PCS to SCK delay: 40 MHz, min. = 46 ns; 66 MHz, min. = 26 ns; 80 MHz min. = 22 ns.
• Spec 3: After SCK delay: 40 MHz, min. = 45 ns; 66 MHz, min. = 25 ns; 80 MHz min. = 21 ns.
• Spec 9: Data setup time for inputs, Master (MTFE = 1, CPHA = 0): 66 MHz, min. = 6 ns; 80 MHz min. = 8 ns.
• Spec 10: Data hold time for inputs, Master (MTFE = 1, CPHA = 0): 40 MHz, min. = 45 ns; 66 MHz, min. = 25 ns;
• Spec 11: Data valid (after SCK edge), Master (MTFE = 1, CPHA = 0): 40 MHz, max. = 45 ns;
• Footnote 1: Changed ‘V
• Footnote 1: Added to beginning of footnote 1 ‘All DSPI timing specifications use the fastest slew rate (SRC =
• Footnote 1: Deleted ‘V
• Footnote 1: Changed ‘V
• Deleted from table title ‘(Pads at 3.3 V or 5.0 V)’
• Deleted 1st line in table ‘CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.’
• Spec 1: FCK frequency -- removed.
• Combined footnotes 1 and 2, and moved the new footnote to Spec 2. Moved old footnote 3 that is now
• Footnote 1, deleted ‘V
• Footnote 2: added ‘cycle’ after ‘duty’ to read: FCK duty cycle is not 50% when . . . .
‘and CL = 200 pF with SRC = 0b11.’
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
speed allowed including frequency modulation (FM). 42 MHz parts allow for 40 MHz system clock + 2% FM;
68 MHz parts allow for 66 MHz system clock + 2% FM, and 82 MHz parts allow for 80 MHz system clock + 2% FM.
max = 3.5 ms; 80 MHz min. = 24.4 ns, max = 2.9 ms.
80 MHz min. = 21 ns.
66 MHz, max. = 25 ns; 80 MHz max. = 21 ns.
0b11) on pad type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew
rate.’
footnote 2 to Spec 2.
Changed ‘CL = 50 pF’ to ‘CL = 25 pF.’
Table 30. Table and Figure Changes Between Rev. 3.0 and 4.0 (continued)
DD
SYS
DD
DDEH
DDEH
DDEH
MPC5534 Microcontroller Data Sheet, Rev. 5
Figure 29
= 1.35–1.65 V’ and ‘V
= 1.35–1.65 V’ and ‘V
= 80 MHz,’ ‘V
= 3.0–5.5;’ to ‘V
= 3.0–5.5;’ to ‘V
= 3.0–5.5;’ to ‘V
MPC5534 324 Package: Deleted the version number and date.
Figure 31
DD
Description of Changes
= 1.35–1.65 V’, ‘V
DDEH
DDEH
DDEH
DD33
DD33
MPC5534 324 Package Dimensions:
= 3.0–5.25;’
= 3.0–5.25;’
= 3.0–5.25;’
and V
and V
DDSYN
DDSYN
DD33
= 3.0–3.6V.’
= 3.0–3.6 V.
and V
DDSYN
= 3.0–3.6 V’ and
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