MPC5534EVBGHS Freescale Semiconductor, MPC5534EVBGHS Datasheet - Page 56

• Manufacturer Part Number: MPC5534EVBGHS
• Description: KIT EVAL GREEN HILLS SOFTWARE
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC5534EVBGHS

• Contents: Eval Board and Demo Software
• Processor To Be Evaluated: MPC55xx
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• Core Architecture: Power
• For Use With/related Products: MPC5534
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision History for the MPC5534 Data Sheet
56
Table
Table
Table
Table
Table
Location
12, FMPLL Electrical Characteristics:
13, eQADC Conversion Specifications: Changed ‘(Operating)’ to ‘(T
14, Flash Program and Erase Specifications:
15, Flash EEPROM Module Life:
16, FLash BIU Settings vs. Frequency of Operations:
• Spec 1, footnote 1 in column 2: ‘PLL reference frequency range’: Added that reads ‘Nominal crystal and external
• Spec 1, footnote 2 in column 1: Changed to: ‘The 8–20 MHz crystal or external reference values have PLLCFG[2]
• Spec 21, column 2: Changed f
• Spec 21: Changed column 5 from ‘f
• Spec 22: Changed column 4, Max Value from f
• Added (T
• Spec 8, 128 KB block pre-program and erase time, Max column value from 15,000 to 7,500.
• Moved footnote 1 from the table title to directly after the ‘Typical’ in the column 5 header.
• Footnote 2: Changed from: ‘Initial factory condition: 100program/erase cycles, 25
• Replaced (Full Temperature Range) with (T
• Spec 1b, Min. column value changed from 10,000 to 1,000.
• ‘Added footnote 1 to the end of the table title, The footnote reads: ‘Illegal combinations exist. Use entries from
• Moved footnote 2:’ For maximum flash performance, set to 0b11’ to the ‘DPFEN’ column header.
• Deleted the x-refs in the ‘DPFEN’ column for the rows.
• Created a x-ref for footnote 2 and inserted in the ‘IPFEN’ column header.
• Deleted the x-refs in the ‘IPFEN’ column for the rows.
• Added to the PFLIM binary values a leading 0 so that 0bxx became 0b0xx.
• Moved footnote 3:’ For maximum flash performance, set to 0b110’ to the ‘PFLIM’ column header.
• Deleted the x-refs in the ‘PFLIM’ column for the rows.
• Moved footnote 4:’ For maximum flash performance, set to 0b1’ to the ‘BFEN’ column header.
• Deleted the x-refs in the ‘BFEN’ column for the rows.
• Added footnotes 4, 6, 7, and 8:
reference values are worst-case not more than 1%. The device operates correctly if the frequency remains within
± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.‘
pulled low’ and applies to spec 1, column 2, crystal reference and external reference.
added the same equation but substituted f
f
f
dual controller (1:1) mode is (f
80 MHz minimum system frequency.‘ To: ‘Initial factory condition: 100program/erase cycles, 25
typical supply voltage measured at a minimum system frequency of 80 MHz.’
the same row in this table.’
ico
ico
-- footnote 4
-- footnote 5
-- footnote 6
-- footnote 7
= [ f
= [ f
Table 30. Table and Figure Changes Between Rev. 3.0 and 4.0 (continued)
ref_crystal
ref_ext
A
= T
 (MFD + 4) ] (PREDIV + 1)
L
– T
 (MFD + 4) ] (PREDIV + 1)
27 MHz parts allow for 25 MHz system clock + 2% frequency modulation (FM).
52 MHz parts allow for 50 MHz system clock + 2% FM.
77 MHz parts allow for 75 MHz system clock + 2% FM.
82 MHz parts allow for 80 MHz system clock + 2% FM.
H
) to the table title.
MPC5534 Microcontroller Data Sheet, Rev. 5
MAX
ref_crystal
2) and the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).’
SYS
’ MHz’ to: ‘f
to f
Description of Changes
ref_ext
ref
A
= T
in ICO frequency equation, and
MAX
for f
L
– T
MAX
to 20, and added footnote 17 to read, ‘Maximum value for
ref
H
’.
) in the table title.
for the external reference clock, giving:
A
= T
L
– T
H
)’ to the table title.
o
C, typical supply voltage,
Freescale Semiconductor
o
C, using a