MPC5554EVBGHS Freescale Semiconductor, MPC5554EVBGHS Datasheet
MPC5554EVBGHS
Specifications of MPC5554EVBGHS
Related parts for MPC5554EVBGHS
MPC5554EVBGHS Summary of contents
Page 1
... The embedded architecture enhancements improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original Power PC instruction set. © Freescale Semiconductor, Inc., 2008. All rights reserved. Document Number: MPC5554 Rev. 3.0, 11/2008 Contents 1 Overview ...
Page 2
... SIU. External interrupts and reset control are also determined by the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing. 2 MPC5554 Microcontroller Data Sheet, Rev. 3.0 Freescale Semiconductor ...
Page 3
... Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and132 MHz parts allow for 128 MHz system clock + 2% FM. Freescale Semiconductor M PC 5554 ...
Page 4
... DDA DDA DD – V –0.3 5.5 RL – V –5.5 5.5 DDA – V –0.3 0.3 SSA – V –V V DDA DDA DDEH – V –0.3 0 Electrical Specifications, Spec 43a. – V –0.1 0.1 SS – V –0.1 0 –2 2 MAXD I –3 3 MAXA T T 150 –55.0 150.0 STG Freescale Semiconductor Unit ...
Page 5
... Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. Freescale Semiconductor 11 and ...
Page 6
... Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device can be obtained from the equation: J × MPC5554 Microcontroller Data Sheet, Rev. 3.0 C/W) 2 Freescale Semiconductor ...
Page 7
... T + (Ψ where thermocouple temperature on top of the package ( T Ψ = thermal characterization parameter ( power dissipation in the package (W) D Freescale Semiconductor × C/W) per JESD51-8 θCA o C/W) o C/W) . For example, change the air flow around the device, θ determine the junction temperature by measuring the ...
Page 8
... Table 4. EMI Testing Specifications Minimum 0.15 — — operating voltages — DDE — — — MPC5554 Microcontroller Data Sheet, Rev. 3.0 Section 2, “Ordering 1 Typical Maximum Unit — 1000 MHz — f MHz MAX 1.5 — V 3.3 — V 5.0 — — 14 dBuV — Freescale Semiconductor ...
Page 9
... RESET pin supply POR DDEH6 voltage RC33 6 Current can be sourced Tj: RCCTL Freescale Semiconductor 1, 2 Table 5. ESD Ratings Symbol R1 C — — — ) and RC and POR electrical specifications: and POR Electrical Specifications RC Characteristic Negated (ramp up) Asserted (ramp down) Asserted (ramp up) Negated (ramp up) ...
Page 10
... DD supply signals 2.2 V. VRCCTL Electrical Specification. DD ÷ the RESET power supplies is required and during power up, V DDSYN stage turn-on to operate RC leads or lags RC33 Freescale Semiconductor Units 1 V/ms — — — — — — 500 — DC Electrical I ). VRCCTL ...
Page 11
... If V propagate the logic signals, the weak-pull devices can pull the signals avoid this condition, minimize the ramp time of the V required to enable the external circuitry connected to the device outputs. Freescale Semiconductor . If V lags V by more than 100 mV, the increase in current ...
Page 12
... RC33 MPC5554 Microcontroller Data Sheet, Rev. 3.0 DD33 or RESET power pin (V DDEH6 can lag V or the RESET power DDSYN lag specification DD33 power supply and the RESET DDSYN V and RESET Power DDSYN V DD Grounded) grounded decreases to less than DD Freescale Semiconductor ) by power DD ...
Page 13
... Load capacitance (fast I/O) DSC (SIU_PCR[8: 0b00 = 0b01 = 0b10 = 0b11 24 Input capacitance (digital pins) 25 Input capacitance (analog pins) 26 Input capacitance: (Shared digital and analog pins AN[12]_MA[0]_SDS, AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK) Freescale Semiconductor 1 = –2 2 MPC5554 Microcontroller Data Sheet, Rev. 3.0 Electrical Characteristics = Symbol Min Max ...
Page 14
... DD_STBY — 1200 DD_STBY — 1500 DD_STBY — 2000 DD_STBY I — (values DD_33 derived from procedure of footnote I — 10 VFLASH I — 15 DDSYN I — 20.0 DD_A I — 1.0 REF I — 25.0 PP Freescale Semiconductor Unit μA μA μA μA μA μA μA μA μ ...
Page 15
... RC33 DDSYN 44 Analog input differential signal range (with common mode 2 Operating temperature range, ambient (packaged) 46 Slew rate on power-supply pins 1 V and V are limited to 2.25–3.6 V only if SIU_ECCR[EBTS DDE2 DDE3 SIU_ECCR[EBTS Freescale Semiconductor MPC5554 Microcontroller Data Sheet, Rev. 3.0 Electrical Characteristics = (continued ...
Page 16
... The and 3.6 V and V = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh. DDE DDEH 125 C. Applies to pad types: pad_a and pad_ae – must be < 0.1 V. SSA0 SSA1 MPC5554 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 17
... Freescale Semiconductor worst-case specification to estimate values at STBY Table 9. Istby vs. Junction Tem Tem p (C) Figure 3. I Worst-case Specifications STBY MPC5554 Microcontroller Data Sheet, Rev. 3.0 Electrical Characteristics ο ...
Page 18
... Freescale Semiconductor ...
Page 19
... These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input pins for the slow and medium pads only. 2 All loads are lumped. Freescale Semiconductor Current Specifications supply dependents on the usage of the pins on all I/O segments. The DD33 ...
Page 20
... DDE5 0.8 3 — 1.5 — 1.5 Refer to crystal Refer to crystal specification specification (2 × – S_EXTAL — 9 – C PCB_EXTAL (2 × – S_XTAL — 9 – C PCB_XTAL — 750 – –4.0 4.0 –2.0 2.0 Freescale Semiconductor Unit MHz MHz ns kHz MHz μ SYS % f SYS ...
Page 21
... Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod). 15 Modulation depth selected must not result in f ÷ RFD sys ico 17 Maximum value for dual controller (1:1) mode is (f Freescale Semiconductor = 3.0–3 0 SSSYN Symbol 13, 14 max: C SYS JITTER 15 C ...
Page 22
... The ADCLK ≥ V due to the presence of the sample RL SSA 9. DC Electrical Specifications, spec 35a) can Freescale Semiconductor Unit MHz ADCLK cycles μ Counts Counts Counts Counts Counts Counts mA Counts Counts ...
Page 23
... Data retention 2 Blocks with 0–1,000 P/E cycles Blocks with 1,001–100,000 P/E cycles 1 Typical endurance is evaluated at 25 information on the Freescale definition of typical endurance, refer to engineering bulletin EB619 Typical Endurance for Nonvolatile Memory. Freescale Semiconductor Symbol 4 T dwprogram T pprogram T 16kpperase ...
Page 24
... V) DDE 4, 5 Rise / Fall Load Drive (ns) (pF 200 200 200 50 260 200 200 200 100 50 125 200 Freescale Semiconductor ...
Page 25
... These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at 1.35–1. 3.0–3 DDE 2 This parameter is supplied for reference and guaranteed by design (not tested). Freescale Semiconductor = 5 DDEH SRC / DSC Out Delay (binary) (ns) ...
Page 26
... To calculate the output delay with respect to the system clock, add a maximum of one Rising-edge Falling-edge out delay out delay Figure 4. Pad Output Delay Characteristic = MPC5554 Microcontroller Data Sheet, Rev. 3.0 ÷ Symbol Min. Max. Unit t 10 — t RPW CYC t 2 — t GPW CYC t 10 — t RCSU CYC t 0 — t RCH CYC Freescale Semiconductor ...
Page 27
... Boundary scan input valid to TCK rising-edge 15 TCK rising-edge to boundary scan input invalid 1 These specifications apply to JTAG boundary scan only. JTAG timing specified at: V Refer to Table 21 for Nexus specifications. Freescale Semiconductor 1 ÷ 2) DDE MPC5554 Microcontroller Data Sheet, Rev. 3.0 Electrical Characteristics Symbol Min ...
Page 28
... Electrical Characteristics TCK 3 TCK TMS, TDI TDO 28 1 Figure 6. JTAG Test Clock Input Timing Figure 7. JTAG Test Access Port Timing MPC5554 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 29
... TCK JCOMP Freescale Semiconductor 9 Figure 8. JTAG JCOMP Timing MPC5554 Microcontroller Data Sheet, Rev. 3.0 Electrical Characteristics 10 29 ...
Page 30
... Electrical Characteristics TCK 11 Output signals 12 Output signals Input signals 30 14 Figure 9. JTAG Boundary Scan Timing MPC5554 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 31
... MDO, MSEO, and EVTO data is held valid until the next MCKO low cycle occurs. 4 Limit the maximum frequency to approximately 16 MHz (V specification for JOV JCYC 5 The RDY pin timing is asynchronous to MCKO and is guaranteed by design to function correctly. MCKO MDO MSEO EVTO Freescale Semiconductor Table 21. Nexus Debug Port Timing 1.35–1. and with DSC = 0b10 2.25– ...
Page 32
... Electrical Characteristics TCK TMS, TDI TDO Figure 11. Nexus TDI, TMS, TDO Timing MPC5554 Microcontroller Data Sheet, Rev. 3.0 12 Freescale Semiconductor ...
Page 33
... WE/BE[0:3] CLKOUT positive edge to output signal valid (output delay) External bus interface CS[0:3] ADDR[8:31] 6 DATA[0:31] BDIP OE RD_WR TA TEA TS TSIZ[0:1] WE/BE[0:3] Freescale Semiconductor Table 22. Bus Operation Timing External Bus Frequency Symbol 40 MHz 56 MHz Min. Max. Min. Max. T 24.4 — 17 45% 55% 45% 55% CDC ...
Page 34
... Table 18 (different values for 1.8 V and 3.3 V). = 2.25–3.6 V only; SIU_ECCR[EBTS timings are tested and DDE MPC5554 Microcontroller Data Sheet, Rev. 3.0 1 (continued Unit 66 MHz Max. Min. Max. — 5.0 — ns — 1.0 — and with DSC = 0b10 Freescale Semiconductor Notes ...
Page 35
... Vol_f CLKOUT CLKOUT 5 Output ÷ DDE bus 5 Output ÷ DDE signal Output signal Freescale Semiconductor Voh_f 3 4 Figure 12. CLKOUT Timing 6 6 Figure 13. Synchronous Output Timing MPC5554 Microcontroller Data Sheet, Rev. 3.0 Electrical Characteristics ÷ DDE ÷ DDE 5 ÷ DDE 5 6 ÷ 2 ...
Page 36
... Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both. 36 ÷ DDE 7 ÷ DDE 7 Figure 14. Synchronous Input Timing Table 23. External Interrupt Timing Symbol t IPWL T IPWH t ICYC = MPC5554 Microcontroller Data Sheet, Rev. 3 Min. Max. Unit 3 — t CYC 3 — t CYC 6 — t CYC Freescale Semiconductor ...
Page 37
... This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). eTPU output eTPU input and TCRCLK Freescale Semiconductor 2 3 Figure 15. External Interrupt Timing Table 24. eTPU Timing = ...
Page 38
... MHz 132 MHz Min. Max. Min. Max. 17.5 ns 2.1 ms 15 — 13 — 14 — 12 — ÷ 2) ÷ 2) ÷ SCK SCK SCK SCK – – — 25 — 25 — 25 — — 4 — 5 — 5 — Freescale Semiconductor Unit t CYC t CYC Unit — ÷ ...
Page 39
... The actual minimum SCK cycle time is limited by pad performance. 5 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. 6 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. 7 This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10. Freescale Semiconductor 1 2 Table 26. DSPI Timing ’ (continued) 80 MHz Symbol Min ...
Page 40
... SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 19. DSPI Classic SPI Timing—Master, CPHA = Last data First data Data 12 First data Data Last data 9 Data First data 12 Data First data MPC5554 Microcontroller Data Sheet, Rev. 3 Last data 11 Last data Freescale Semiconductor ...
Page 41
... SCK input (CPOL=1) SOUT SIN Figure 20. DSPI Classic SPI Timing—Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) SOUT SIN Figure 21. DSPI Classic SPI Timing—Slave, CPHA = 1 Freescale Semiconductor First data Data Last data 9 10 Data Last data First data ...
Page 42
... SCK output (CPOL=1) SIN SOUT Figure 23. DSPI Modified Transfer Format Timing—Master, CPHA = First data Last data Data 12 11 First data Last data Data 9 First data Data 12 First data Data MPC5554 Microcontroller Data Sheet, Rev. 3 Last data 11 Last data Freescale Semiconductor ...
Page 43
... SIN Figure 24. DSPI Modified Transfer Format Timing—Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) SOUT SIN Figure 25. DSPI Modified Transfer Format Timing—Slave, CPHA = 1 PCSS PCSx Freescale Semiconductor First data Data Last data 10 9 Data First data Last data ...
Page 44
... Figure 27. EQADC SSI Timing MPC5554 Microcontroller Data Sheet, Rev. 3.0 Typical Maximum — × 6.5) — SYS_CLK 8 × 6.5) — SYS_CLK — +7.5 — +7.5 — — — — 4 25th 5 2nd 26th 25th 26th Freescale Semiconductor Unit t SYS_CLK ...
Page 45
... VSS VDD DATA DATA DATA DATA GPIO AF VSS VDD VDDE2 206 Freescale Semiconductor show the pinout for the MPC5554 416 PBGA package. NOTE ETRIG VRH AN23 AN27 AN28 AN35 VSSA0 AN15 1 REF ETRIG AN22 AN26 AN31 AN32 VSSA0 AN14 BYPC 0 ETPUB ...
Page 46
... VDDE2 VDDE2 VSS VSS VDDE2 VDDE2 VSS VSS VDDE2 VDDE2 VSS VSS VDDE2 VSS VDDE2 VDDE2 VSS VDDE2 VDDE2 VDDE2 DATA DATA DATA DATA VDDE2 GPIO DATA DATA DATA VDD33 207 DATA DATA DATA DATA DATA DATA DATA VDDE2 Freescale Semiconductor ...
Page 47
... EMIOS EMIOS DATA EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS Figure 30. MPC5554 416 Package Right Side (view Freescale Semiconductor ETPUB ETPUB ETPUB GPIO MDO11 MDO8 205 ETPUB ETPUB ETPUB MDO10 MDO7 ETPUB ETPUB MDO9 MDO6 MDO3 26 30 ETPUB ETPUB ...
Page 48
... Mechanicals 4.2 MPC5554 416-Pin Package Dimensions The package drawings of the MPC5554 416 pin TEPBGA package are shown in 48 Figure 31. MPC5554 416 TEPBGA Package MPC5554 Microcontroller Data Sheet, Rev. 3.0 Figure 31. Freescale Semiconductor ...
Page 49
... Figure 31. MPC5554 416 TEPBGA Package (continued) Freescale Semiconductor MPC5554 Microcontroller Data Sheet, Rev. 3.0 Mechanicals 49 ...
Page 50
... BGA diagram, the muxed and GPIO signals on those pins remain available. See the signals chapter in the device reference manual for the signal muxing. 50 Table 28. Changes Between Rev. 2.0 and 3.0 Description of Changes = .’ Grounded)” NOTE MPC5554 Microcontroller Data Sheet, Rev. 3.0 Freescale Semiconductor ...
Page 51
... Footnote 1: Removed V • Footnote 8: Changed EBTS to SIU_ECCR[EBTS]. Table 23 External Interrupt Timing (IRQ Signals) • Footnote 1: Removed V Table 24 eTPU Timing • Footnote 1: Changed V Table 25 eMIOS Timing • Footnote 1: Changed V Freescale Semiconductor Description of Changes Table 9 and V are limited to 2.25–3.6 V only if SIU_ECCR[EBTS DDE2 DDE3 = ...
Page 52
... MHz maximum column from 2.0 to 2.1. Table 27 EQADC SSI Timing Characteristics • Footnote 1: Changed V 52 Description of Changes = 3.0–5.5 V;’ to ‘V = 3.0–5.25 V;’ DDEH DDEH = 3.0–5 3.0–5.25 V. DDEH DDEH MPC5554 Microcontroller Data Sheet, Rev. 3.0 Freescale Semiconductor ...
Page 53
... Freescale Semiconductor MPC5554 Microcontroller Data Sheet, Rev. 3.0 Revision History for the MPC5554 Data Sheet 53 ...
Page 54
... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...