MPC5554EVBGHS Freescale Semiconductor, MPC5554EVBGHS Datasheet - Page 12

• Manufacturer Part Number: MPC5554EVBGHS
• Description: BOARD EVAL GREEN HILLS SOFTWARE
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC5554EVBGHS

• Contents: Eval Board and Demo Software
• Processor To Be Evaluated: MPC55xx
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• Core Architecture: Power
• For Use With/related Products: MPC5554
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
3.7.1
When powering up the device, V
more than the V
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. V
pin (V
applies during power up only. V
3.7.2
The 1.5 V V
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, V
POR negate.
3.7.3
The only requirement for the power-down sequence with V
its operating range, V
increases to its operating range. This ensures that the digital 1.5 V logic, which is reset only by an ORed
POR and can cause the 1.5 V supply to decrease less than its specification value, resets correctly. See
Table
12
6, footnote 1.
DDEH6
Input Value of Pins During POR Dependent on V
Power-Up Sequence (V
Power-Down Sequence (V
DD
), but cannot lag both by more than the V
power supply must rise to 1.35 V before the 3.3 V V
DD33
V
DD
2.0 V
must reach 1.35 V before V
DDSYN
lag specification listed in
Figure 2. Power-Up Sequence (V
or the RESET power must decrease to less than 2.0 V before the V
DD33
MPC5554 Microcontroller Data Sheet, Rev. 3.0
DD33
DD
1.35 V
has no lead or lag requirements when powering down.
must be within specification before the 3.3 V POR and the RESET
must not lag the latest V
DDSYN
RC33
Table
RC33
and the RESET power reach 2.0 V
Grounded)
DD33
6, spec 8. This avoids accidentally selecting the
Grounded)
lag specification. This V
RC33
DD33
RC33
DDSYN
grounded is if V
Grounded)
V
can lag V
DDSYN
DDSYN
or RESET power pin (V
and RESET Power
power supply and the RESET
DDSYN
V
DD33
DD
DD
DD33
or the RESET power
decreases to less than
Freescale Semiconductor
lag specification
DDEH6
DD
power
) by