SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet
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... Introduction to the Quartus II Software ® Version 10.0 ...
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... Introduction to the ® ® Altera Corporation 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Quartus Software II ® ...
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... AMBA is a trademark of ARM, Limited. Mentor Graphics and ModelSim are registered trademarks of Mentor Graphics Corporation. Altera reserves the right to make changes, without notice, in the devices or the device specifications identified in this document. Altera advises its customers to obtain the latest version of device specifications to verify, before placing orders, that the information being relied upon by the customer is current. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’ ...
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... Using the Quartus II Symbol Editor.............................................................. 22 Using the Quartus II Text Editor.................................................................... 23 Using Verilog HDL, VHDL, & AHDL........................................................... 23 Using the State Machine Editor ..................................................................... 24 Using Altera Megafunctions......................................................................................... 24 Using Intellectual Property (IP) Megafunctions.......................................... 25 Using the MegaWizard Plug-In Manager..................................................... 27 Instantiating Megafunctions in the Quartus II Software............................ 27 Instantiation in Verilog HDL & VHDL........................................... 28 Using the Port & ...
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T C ABLE OF ONTENTS The RTL Viewer ................................................................................................ 45 The State Machine Viewer .............................................................................. 47 The Technology Map Viewer.......................................................................... 48 Chapter 4: Place and Route.......................................................................................................... 51 Introduction..................................................................................................................... 52 Using Incremental Compilation ................................................................................... 53 Analyzing Fitting Results .............................................................................................. 54 Using ...
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... Chapter 9: System Requirements, Licensing & Technical Support ..................................... 117 Installing the Quartus II Software.............................................................................. 118 Licensing the Quartus II Software ............................................................................. 119 Getting Technical Support........................................................................................... 119 Getting Online Help..................................................................................................... 121 Starting the Quartus II Interactive Tutorial .............................................................. 122 Other Quartus II Software Documentation .............................................................. 123 Other Altera Literature ................................................................................................ 124 Documentation Conventions .................................................................................................... 125 A C LTERA ORPORATION I ...
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T C ABLE OF ONTENTS I ■ VI NTRODUCTION TO THE UARTUS OFTWARE A C LTERA ORPORATION ...
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... Preface This manual is designed for the novice Altera user and provides an overview of the capabilities of the Quartus II software in programmable logic design. The Altera Quartus II software is the most comprehensive environment available for system-on-a-programmable-chip (SOPC) design not, however, intended exhaustive reference manual for the Quartus II software. Instead guide that explains the features of the software and how these can assist you in FPGA and CPLD design ...
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T C ABLE OF ONTENTS I ■ VIII NTRODUCTION TO THE UARTUS OFTWARE A C LTERA ORPORATION ...
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What’s in Chapter 1: Introduction Graphical User Interface Design Flow 3 Command-Line Executables Design Methodologies and Planning 14 Chapter Design Flow 2 7 One ...
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... ESIGN LOW I NTRODUCTION Introduction The Altera Quartus II design software provides a complete, multiplatform design environment that easily adapts to your specific design needs comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes solutions for all phases of FPGA and CPLD design Figure 1. Quartus II Design Flow ...
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... Graphical User Interface Design Flow You can use the Quartus II software graphical user interface (GUI) to perform all stages of the design flow. it appears when you first start the software. Figure 2. Quartus II Graphical User Interface The Quartus II software includes a modular Compiler. The Compiler ...
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... Figure 3. Tasks Window The Quartus II software also provides other predefined compilation flows that you can use with commands on the Processing menu. commands for some of the most common compilation flows. ...
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... To create a new project and specify a target device or device family, on the File menu, click New Project Wizard. 2. Use the Text Editor to create a Verilog HDL, VHDL, or Altera Hardware Description Language (AHDL) design. 3. Use the Block Editor to create a block diagram with symbols that represent other design files create a schematic ...
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... Use physical synthesis, the Chip Planner, LogicLock regions, and the Assignment Editor to correct timing problems. 15. Create programming files for your design with the Assembler, and then program the device with the Programmer and Altera programming hardware. 16. (Optional) Debug the design with the SignalTap external logic analyzer, the SignalProbe feature, or the Chip Planner ...
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... Command-Line Executables The Quartus II software includes separate executables for each stage of the design flow. Each executable occupies memory only while it is running. You can use these executables with standard command-line commands and scripts, with Tcl scripts, and in makefiles. See command-line executables. ...
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HAPTER ESIGN LOW OMMAND INE XECUTABLES Table 2. Command-Line Executables (Part Executable Title Name quartus_map Analysis & Synthesis quartus_fit Fitter quartus_drc Design Assistant quartus_sta TimeQuest Timing Analyzer quartus_asm Assembler quartus_eda ...
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... Assembler, the SignalTap II Logic Analyzer captures signals from internal device nodes while the device is running at speed. Estimates and reports the simultaneous switching noise contributions to voltage and timing noise for device pins. Provides overall control of Quartus II projects and compilation flows, as well as a Tcl shell. ...
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... Analysis & Synthesis, perform place and route, perform timing analysis, and generate programming files for the filtref design that is included with the Quartus II software. If you have installed the filtref design the /altera/ <version number>/qdesigns/fir_filter directory. You can run the four commands in directory, or you can store them in a batch file or shell script ...
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... The Quartus II software also supports makefile scripts that use the Quartus II executables, which allow you to integrate your scripts with a wide variety of scripting languages LTERA ORPORATION FILES_WITH_ERRORS=" ...
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... Using command-line executables Using compilation flows Using Tcl Commands There are several ways to use Tcl scripts in the Quartus II software. You can create a Tcl script by using commands from the Quartus II API for Tcl. You should save a Tcl script as a Tcl Script File (.tcl). ...
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Figure 7 shows an example of a Tcl script. Figure 7. Example of a Tcl Script ## This script works with the quartus_sh executable # Set the project name to filtref set project_name filtref # Open the Project ...
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... Compiling all design partitions in a single Quartus II project ensures that all design logic is compiled with a consistent set of assignments and allows the software to perform global placement and routing optimizations. Compiling all design logic together is beneficial for FPGA design flows because in the end all parts of the design must use the same shared set of device resources. ...
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... Using LogicLock Regions A LogicLock region is defined by its size and location on the device. You can specify the size and location of a region, or direct the Quartus II software to create them automatically. With the LogicLock design flow, you can define a hierarchy for a group of regions by declaring parent and child regions. The Quartus II software places child regions completely within the boundaries of a parent region ...
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... LogicLock regions from them, or drag them into an existing LogicLock region in the Timing Closure Floorplan. Altera also provides LogicLock Tcl commands to assign LogicLock region content at the command line or in the Quartus II Tcl Console window. You can use the provided Tcl commands to create floating and auto-size ...
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... After the initial or setup compilation, Altera recommends that you set the Size to Fixed in order to yield better f increasing the size of the LogicLock region may allow the Fitter additional flexibility in placement and may produce better final results. When you perform an incremental compilation, the fitting and synthesis results and settings for design partitions are saved in the project database ...
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HAPTER ESIGN LOW ESIGN ETHODOLOGIES AND LANNING 18 ■ I NTRODUCTION TO THE UARTUS OFTWARE A C LTERA ORPORATION ...
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... What’s in Chapter 2: Introduction Creating a Project Creating a Design Using Altera Megafunctions Constraint Entry Chapter Design Entry Two ...
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... Files generated by the MegaWizard Plug-In Manager Block Symbol Files (.bsf) Quartus II Symbol Editor The Quartus II software also supports system-level design entry flows with the Altera SOPC Builder and DSP Builder software. For more information about these methods, refer to page 199. 20 ■ I ...
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Creating a Project You can create a new project by clicking New Project Wizard on the File menu. When creating a new project, you specify the working directory for the project, assign the project name, and designate the name of ...
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... Each Symbol Editor file represents one symbol. For each symbol file, you can choose from libraries containing Altera megafunctions. You can customize these Block Symbol Files and then add the symbols to schematics created with the Block Editor. ...
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... Design Files, Verilog Design Files, and VHDL Design Files, and combine them with other types of design files in a hierarchical design. Verilog Design Files and VHDL Design Files can contain any combination of Quartus II–supported constructs. They can also contain Altera-provided logic functions, including primitives and megafunctions, and user-defined logic functions. ...
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... LVDS drivers, PLLs, and SERDES and DDIO circuitry. You can use the MegaWizard Plug-In Manager on the Tools menu to create Altera megafunctions, LPM functions, and IP functions for use in designs in the Quartus II software and EDA design entry and synthesis tools. shows the types of Altera-provided megafunctions and LPM functions that you can create with the MegaWizard Plug-In Manager ...
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... Megafunctions Altera provides several methods for obtaining both Altera Megafunction Partners Program (AMPP are rigorously tested and optimized for the highest performance in Altera device-specific architectures. You can use these parameterized blocks of intellectual property to reduce design and test time. MegaCore and AMPP ...
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... MegaCore functions are automatically installed when you install the Quartus II software. You can also download individual IP MegaCore functions from the Altera website, via the IP MegaStore, and install them separately. You can also access MegaCore functions though the MegaWizard Portal Extension to the MegaWizard Plug-In Manager. ...
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... MegaWizard Plug-In Manager to parameterize the megafunction and create a wrapper file), or through inference. Altera recommends that you use the MegaWizard Plug-In Manager to instantiate megafunctions and create custom megafunction variations. The wizard provides a GUI for customizing and parameterizing megafunctions, and ensures that you set all megafunction parameters correctly ...
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... Quartus II Analysis & Synthesis automatically recognizes certain types of HDL code and infers the appropriate megafunction. The Quartus II software uses inference because Altera megafunctions are optimized for Altera devices, and performance may be better than standard HDL code. For some architecture-specific features, such as RAM and DSP blocks, you must use Altera megafunctions ...
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... Altera megafunction during synthesis. Using the Clear Box Methodology In the black box flow, an EDA synthesis tool treats Altera megafunctions and LPM functions as black boxes result, the EDA synthesis tool cannot fully synthesize and optimize designs with Altera megafunctions, because the tool does not have a full model or timing information for the function ...
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... LTERA EGAFUNCTIONS Using the clear box flow, you can use the MegaWizard Plug-In Manager to create a fully synthesizeable Altera megafunction or LPM function for use with EDA synthesis tools. The following steps describe the basic flow for using clear box megafunctions with EDA synthesis tools: 1 ...
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... Quartus II Help Command-Line Scripting chapter in volume 2 of the Quartus II Handbook AN 343: OpenCore Evaluation of AMPP Megafunctions on the Altera website AN 320: OpenCore Plus Evaluation of Megafunctions on the Altera website Simulating Altera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook I Q NTRODUCTION TO THE UARTUS ...
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... When creating and editing assignments, the Quartus II software dynamically validates the assignment information where possible assignment or assignment value is illegal, the Quartus II software does not add or update the value, and instead reverts to the current value or does not accept the value. When you view all assignments, the Assignment Editor 32 ■ ...
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Assignment Editor displays only the assignments that are related to the specific category selected. f For Information ...
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HAPTER ESIGN NTRY C E ONSTRAINT NTRY Figure 4. Pin Planner By default, the Pin Planner displays a Groups list, an All Pins list, and a package view diagram of the device. You can make pin ...
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For Information About Using the Pin Planner to assign pins The Settings Dialog Box You can use the Settings dialog box to specify general project-wide options and synthesis, fitting, simulation, timing analysis, power analysis, and debugging options for a ...
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HAPTER ESIGN NTRY C E ONSTRAINT NTRY ■ Specify Design Assistant and SignalTap II settings: enable the Design Assistant and enable the SignalTap II Logic Analyzer; specify a SignalTap II File (.stp) name. f For Information ...
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Post-Fit—preserves placement results for the partition ■ Empty—skips compilation for the partition You can specify the netlist type from the list in the Netlist Type column or by right-clicking the partition and clicking Design Partition Properties. If you want ...
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HAPTER ESIGN NTRY C E ONSTRAINT NTRY Figure 5. Design Partition Planner f For Information About Assigning design partitions and using incremental compilation 38 ■ I NTRODUCTION TO THE Refer To Quartus II Incremental Compilation for ...
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What’s in Chapter 3: Introduction Using Quartus II Verilog HDL & VHDL Integrated Synthesis Using the Design Assistant to Check Design Reliability Analyzing Synthesis Results With the Netlist Viewers Chapter Three Synthesis ...
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... Verilog Quartus Mapping files (.v, .vhd) Files (.vqm) You can start a full compilation in the Quartus II software, which includes the Analysis & Synthesis module, or you can start Analysis & Synthesis separately. You can perform an Analysis & Elaboration to check a design for syntax and semantic errors without performing a complete Analysis & ...
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... Verilog-2001 and VHDL 1993 by default. If you are using another EDA synthesis tool, you can also specify a Library Mapping File (.lmf) that the Quartus II software should use to map non–Quartus II functions to Quartus II functions. You can specify these and other options in the Verilog HDL Input and VHDL Input pages, which are under Analysis & ...
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... For Information About Quartus II Verilog HDL and VHDL Synthesis support If your design instantiates Altera megafunctions, library of parameterized modules (LPM) functions, or intellectual property (IP) megafunctions in a third-party EDA tool, you need to use a hollow-body or black box file. When you are instantiating megafunctions for Quartus II Analysis & Synthesis, however, you can instantiate the megafunction directly without using a black box file ...
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... Optimization Options Quartus II synthesis optimization options allow you to optimize the netlist during synthesis for many of the Altera device families. These optimization options are additional to the optimization that occurs during a standard compilation, and occur during the Analysis & Synthesis stage of a full compilation ...
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HAPTER YNTHESIS SING THE ESIGN SSISTANT TO f For Information About Using Quartus II synthesis and netlist optimization options Using the Design Assistant to Check Design Reliability The Quartus II Design Assistant allows you ...
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... ESULTS Refer To “Analyzing Designs with the Design Assistant” and “About the Design Assistant” in Quartus II Help Design Recommendations for Altera Devices and the Quartus II Design Assistant, Recommended HDL Coding Styles, and Quartus II Integrated Synthesis chapters in volume 1 of the Quartus II Handbook “ ...
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HAPTER YNTHESIS NALYZING YNTHESIS ESULTS Figure 2. RTL Viewer The RTL Viewer displays the Analysis & Elaboration results for Verilog HDL or VHDL designs, and AHDL Text Design Files (.tdf), Block Design Files ...
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The State Machine Viewer The State Machine Viewer allows you to view state machine diagrams for the relevant logic in your design. If your project has a state machine, on the Tools menu, point to Netlist Viewers, and then click ...
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HAPTER YNTHESIS NALYZING YNTHESIS ESULTS Figure 4. State Machine Viewer When you select a cell in a transition table, the corresponding state or transition is highlighted in the schematic view. Likewise, when you ...
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Viewer by pointing to Netlist Viewers on the Tools menu, and then clicking Technology Map Viewer. The Technology Map Viewer includes a schematic view, and also includes a hierarchy list, which lists the instances, primitives, pins, and nets for the ...
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HAPTER YNTHESIS NALYZING YNTHESIS ESULTS Viewer; see “Analyzing Synthesis Results With the Netlist Viewers” on page 45. The tooltips in the Technology Map Viewer display equation information as well as node and source ...
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What’s in Chapter 4: Introduction Using Incremental Compilation Analyzing Fitting Results Optimizing the Fit Chapter Place and Route Four ...
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... Introduction The Quartus II Fitter places and routes your design, which is also referred to as “fitting” in the Quartus II software. Using the database that has been created by Analysis & Synthesis, the Fitter matches the logic and timing requirements of the project with the available resources of the target device. ...
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... You can start a full compilation in the Quartus II software, which includes the Fitter module, or you can start the Fitter separately. You must run Analysis & Synthesis successfully before starting the Fitter separately. For information about performing a full compilation, refer to Interface Design Flow” on page 3 in Chapter 1, “Design Flow.” ...
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... Using Quartus II incremental compilation Analyzing Fitting Results The Quartus II software offers several tools to help you analyze the results of compilation and fitting. The Messages window and Report window provide fitting results information. The Chip Planner allows you to view fitting results and make adjustments, if necessary. In addition, the Design Assistant helps you check the reliability of a design based on a set of design rules ...
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Using the Messages Window to View Fitting Results The Processing tab of the Messages window and the Messages section of the Report window or Report File display the messages generated from the most recent compilation or simulation. Figure 2. Messages ...
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... Fitter, as well as messages for any other module you were running. The Quartus II software automatically generates text and HTML versions of reports, depending on which options you specify in the Processing page of the Options dialog box. ...
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Figure 3. Chip Planner Resource usage in the Chip Planner is color coded. Different colors represent different resources, such as unassigned and assigned pins and logic cells, unrouted items, and row FastTrack you to customize the floorplan view using filters ...
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HAPTER LACE AND OUTE O F PTIMIZING THE IT You can view the routing congestion in a design, view routing delay information for paths, and view connection counts to specific nodes. The Chip Planner also allows ...
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... Fitter effort to only one attempt, which may also reduce the f Setting Physical Synthesis Optimization Options The Quartus II software allows you to set options for performing physical synthesis to optimize the netlist during fitting. You specify physical synthesis optimization options in the Physical Synthesis Optimizations page under Compilation Process Settings page in the Settings dialog box ...
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HAPTER LACE AND OUTE O F PTIMIZING THE IT For more information about physical synthesis options, refer to Netlist Optimizations to Achieve Timing Closure” on page 142 in Chapter 10, “Timing Closure.” f For Information About ...
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DSP blocks ■ I/O elements ■ Routing resources If you have an open project, you can view the Resource Optimization Advisor by clicking Resource Optimization Advisor on the Tools menu. If the project has not been compiled yet, the ...
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... If the recommended action involves changing a Quartus II setting, the right pane of the Resource Optimization Advisor may include a link to the appropriate dialog box, page, or feature in the Quartus II software or may include a button that provides more information about the design. It may also include links to Quartus II Help or other documentation on the Altera website. 62 ■ ...
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If you want to view recommendations for improving timing results, you can use the Timing Optimization Advisor. See Advisor” on page 141 in Chapter 10, “Timing Closure.” Using the Design Space Explorer Another way to control Quartus II fitting to ...
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... After you have completed a design exploration with DSE, you can create a new revision from a DSE point. You can then close DSE and open the project with the new revision from within the Quartus II software. f For Information About Parameters and settings for optimizing ...
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What’s in Chapter 5: Introduction Running the TimeQuest Timing Analyzer Timing Closure Chapter Timing Analysis and Design Optimization Five ...
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HAPTER IMING NALYSIS AND I NTRODUCTION Introduction The Quartus II TimeQuest Timing Analyzer allows you to analyze the timing characteristics of your design. The TimeQuest analyzer uses industry-standard Synopsys Design Constraint (SDC) methodology for constraining designs ...
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Figure 1. TimeQuest Timing Analyzer Window Report pane View pane Tasks pane Console The View pane displays timing analysis results, including any summary reports, custom reports, or histograms. you use the Report Clocks command in the Tasks pane for a ...
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... False paths—You can designate as false paths any paths in the design which the timing analyzer disregards during analysis and reporting. By default, the Quartus II software cuts (directs the timing analyzer to 68 ■ I NTRODUCTION TO THE ...
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... The Quartus II software also cuts paths between unrelated clock domains if individual clock assignments are set but there is no defined relationship between the clock assignments. ...
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... For Information About Specific timing settings and performing a timing analysis in the Quartus II software Viewing Timing Information for a Path You can use the Report Timing dialog box to generate comprehensive timing information for any path or paths in your design. You can specify the number of paths to report, the type of path (including minimum timing paths), and how to report the information ...
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Figure 3. Report Timing Dialog Box When information about a path is reported by the TimeQuest analyzer, you can use the Locate Path command directly from the timing analyzer reports to view path information in the Chip Planner, Technology Map ...
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HAPTER IMING NALYSIS AND UNNING THE IME UEST IMING Viewing Timing Delays with the Technology Map Viewer The Quartus II Technology Map Viewer provides a low-level, or atom-level, technology-specific schematic representation a ...
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... Using the Quartus II Technology Map Viewer Timing Closure The Quartus II software offers a fully integrated timing closure flow that allows you to meet your timing goals by controlling the synthesis and place and route of a design. Using the timing closure flow results in faster timing closure for complex designs, reduced optimization iterations, and automatic balancing of multiple design constraints ...
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HAPTER IMING NALYSIS AND T C IMING LOSURE Using the Chip Planner You can use the Chip Planner to view logic placement made by the Fitter, view user assignments and LogicLock region assignments, and routing information ...
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... Using Netlist Optimizations to Achieve Timing Closure The Quartus II software includes netlist optimization options to further optimize your design during synthesis and during place and route. Netlist optimizations are push-button features that offer improvements to f results by making modifications to the netlist to improve performance. ...
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... WYSIWYG primitives during synthesis. When this option is turned on, the Quartus II software unmaps the logic elements in an atom netlist to gates, and remaps the gates to Altera LCELL primitives. This option allows the Quartus II software to use techniques specific to a device architecture during the remapping process and uses the optimization technique (Speed, Balanced, or Area). ■ ...
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... The Quartus II software cannot perform these netlist optimizations for fitting and physical synthesis on a back-annotated design. In addition, if you use one or more of these netlist optimizations on a design, and then back-annotate the design, you must generate a Verilog Quartus Mapping File ( ...
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... The PowerPlay Power Analyzer performs postfitting power analysis and produces a power report that highlights, by block type and entity, the power consumed. The Altera PowerPlay Early Power Estimator estimates power consumption at other stages of the design process and produces a Microsoft Excel-based spreadsheet with estimate information ...
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... In addition, you can specify entity-based toggle rates and static probabilities using user assignments in the Quartus II user interface or in the Quartus II Settings File (.qsf). For some device families, the Quartus II software fills in any missing signal activity information by analyzing the design topology and function. A ...
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... You can calculate power requirements for certain device families with the Altera PowerPlay Early Power Estimator spreadsheets, which you can download from the Power Consumption section of the Altera website. If you have not started the FPGA design only partially complete, you can use PowerPlay Early Power Estimator spreadsheets to provide a preliminary estimate of the power requirements of the design ...
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... You can use the PowerPlay Early Power Estimator to estimate power at any stage of the design process; however, Altera recommends that you use the PowerPlay Power Analyzer, rather than the PowerPlay Early Power Estimator, after the design is complete in order to obtain the most accurate power analysis ...
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HAPTER IMING NALYSIS AND T C IMING LOSURE 82 ■ I NTRODUCTION TO THE D O ESIGN PTIMIZATION UARTUS OFTWARE A C LTERA ORPORATION ...
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What’s in Chapter 6: Introduction Creating and Using Programming Files Chapter Programming & Configuration 84 85 Six ...
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... NTRODUCTION Introduction Once you have successfully compiled a project with the Quartus II software, you can program or configure an Altera device. The Assembler module of the Quartus II Compiler generates programming files that the Quartus II Programmer can use to program or configure a device with Altera programming hardware. You can also use a stand-alone version of the Quartus II Programmer to program and configure devices ...
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... The Programmer uses the Programmer Object Files and SRAM Object Files generated by the Assembler to program or configure all Altera devices supported by the Quartus II software. You use the Programmer with Altera programming hardware, such as the MasterBlaster ByteBlaster ™ ...
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& C HAPTER ROGRAMMING REATING AND SING ROGRAMMING The Programmer allows you to create a Chain Description File (.cdf) that contains the name and options of devices used for a design. You can also ...
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... Active Serial ■ In-Socket The Passive Serial and JTAG programming modes allow you to program single or multiple devices using a Chain Description File and Altera programming configuration device using Active Serial Programming mode and Altera programming hardware. You can program a single CPLD or configuration device using In-Socket Programming mode with a Chain Description File and Altera programming hardware ...
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... Refer To MasterBlaster Serial/USB Communications Cable User Guide, ByteBlaster II Download Cable User Guide, ByteBlasterMV Download Cable User Guide, USB-Blaster Download Cable User Guide, and EthernetBlaster Communications Cable User Guide on the Altera website The Configuration Handbook on the Altera website UARTUS OFTWARE A C LTERA ...
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What’s in Chapter 7: Introduction Using the SignalTap II Logic Analyzer Using an External Logic Analyzer Using SignalProbe Using the In-System Memory Content Editor Using the In-System Sources and Probes Editor Using the RTL Viewer & Technology Map Viewer For ...
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... NTRODUCTION TO THE NGINEERING HANGE ANAGMENT show the SignalTap II and SignalProbe debugging Partition Merge quartus_cdb -- merge Quartus II Fitter Quartus II Assembler quartus_fit Altera Device SignalTap II Logic Analyzer UARTUS OFTWARE quartus_asm Programming Quartus II Files Programmer quartus_pgm View data in the Quartus II software via the JTAG programming interface ...
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... SignalTap II Logic Analyzer as waveforms. Figure 3 on page LTERA ORPORATION HAPTER EBUGGING AND U SING THE SignalProbe Compilation quartus_fit Programming Files Altera Device shows the SignalTap II Logic Analyzer. I NTRODUCTION TO THE NGINEERING HANGE ANAGMENT IGNAL AP OGIC NALYZER Quartus II Assembler ...
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HAPTER EBUGGING AND SING THE IGNAL AP OGIC Figure 3. The SignalTap II Logic Analyzer Analyzing SignalTap II Data When you use the SignalTap II Logic Analyzer to view the results ...
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For Information About Using the SignalTap II Logic Analyzer Using an External Logic Analyzer The Logic Analyzer Interface is logic within the device you use to connect a large set of internal device signals to a small number of ...
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HAPTER EBUGGING AND SING IGNAL ROBE Using SignalProbe The SignalProbe feature allows you to route user-specified signals to output pins without affecting the existing fitting in a design, so that you can debug signals ...
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The In-System Memory Content Editor captures and updates data in the device. You can export or import data in Memory Initialization File (.mif), Hexadecimal (Intel-Format) File (.hex), and RAM Initialization File (.rif) formats. The In-System Memory Content Editor offers the ...
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HAPTER EBUGGING AND SING THE N YSTEM OURCES AND Using the In-System Sources and Probes Editor The In-System Sources and Probes Editor allows you to control all of the altsource_probe megafunction instances within ...
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For Information About Using the In-System Sources and Probes Editor Using the RTL Viewer & Technology Map Viewer For Debugging You can use the RTL Viewer to analyze your design after analysis and elaboration is complete. The RTL Viewer ...
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... I/O element, or PLL atoms, without requiring a full recompilation. The Quartus II software allows you to make small modifications, often referred to as engineering change orders (ECO design after a full compilation. These ECO changes can be made directly to the design database, rather than to the source code or the Quartus II Settings File ( ...
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Use the Start Check & Save All Netlist Changes command on the Processing menu to check the legality of the change for all of the other resources in the netlist. 7. Run the Assembler to generate a new programming ...
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HAPTER EBUGGING AND SING THE HIP LANNER FOR EBUGGING Figure 5. Chip Planner You can then use the information from the Chip Planner to determine which properties and settings you may want to ...
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M Modifying Resource Properties With the Resource Property Editor The Resource Property Editor allows you to make post-compilation edits to the properties and parameters of logic cell, I/O element, or PLL resources, as well as edit or remove connections for ...
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HAPTER EBUGGING AND ODIFYING ESOURCE ROPERTIES Figure 6. Resource Property Editor Viewer shows schematic diagram of resource Connectivity panel shows the input and output ports The Resource Property Editor allows you to right-click a ...
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Assembler. You can also view a summary of your changes in the Change Manager. Refer to the next section, with the Change f For Information About Engineering change management and using the Resource Property Editor Viewing & Managing ...
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HAPTER EBUGGING AND V & IEWING ANAGING HANGES WITH THE Verifying ECO Changes After you have made an ECO change, you should run the Assembler module of the Compiler to create a new Programmer Object ...
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What’s in Chapter 8: Introduction EDA Synthesis Tools EDA Simulation Tools Timing Analysis with EDA Tools Formal Verification Chapter EDA Tool Support 106 108 109 112 114 Eight ...
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... EDA T S HAPTER OOL UPPORT I NTRODUCTION Introduction The Quartus II software allows you to use the EDA tools you are familiar with for various stages of the design flow, including synthesis, simulation, and formal verification. Figure 1. EDA Tool Design Flow Quartus II Analysis & Synthesis Quartus II ...
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... Quartus II-supported EDA formal verification tools to make sure that Quartus II post-fit netlist is equivalent to that of the synthesized netlist. 9. Program the device with the Programmer and Altera hardware. ! Using the quartus_eda executable You can also run the EDA Netlist Writer to generate the necessary output files separately at the command prompt script by using the quartus_eda executable ...
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... LeonardoSpectrum Mentor Graphics Precision RTL Synthesis Synopsys Synplify Synopsys Synplify Pro Magma Blast FPGA Cadence Incisive Enterprise Simulator Mentor Graphics ModelSim Mentor Graphics ModelSim-Altera Mentor Graphics QuestaSim Synopsys VCS MX Synopsys VCS Aldec Active-HDL Mentor Graphics Tau (through Stamp) Synopsys PrimeTime Cadence Encounter Conformal ...
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... Altera provides libraries for use with many EDA synthesis tools. Altera also provides NativeLink support for many tools. NativeLink technology facilitates the seamless transfer of information between the Quartus II software and other EDA tools and allows you to run EDA tools automatically from within the Quartus II graphical user interface. ...
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... You can run the EDA Netlist Writer module to generate Verilog Output Files and VHDL Output Files by specifying EDA tool settings and compiling the design. If you have already compiled a design in the Quartus II software, you can specify different simulation output settings in the Quartus II ...
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... Altera-specific components, and atom-based timing simulation libraries for designs compiled in the Quartus II software. You can use these libraries to perform functional or timing simulation of any design with Altera-specific components in EDA simulation tools that are supported by the Quartus II software. Additionally, Altera provides pre-compiled functional and timing simulation libraries for simulation in the ModelSim-Altera software ...
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... The timing simulation library files differ based on device family and whether you are using Verilog Output Files or VHDL Output Files. For VHDL designs, Altera provides VHDL Component Declaration files for designs with Altera-specific megafunctions. f ...
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... Assignments menu, or during project setup, with the New Project Wizard on the File menu. 2. Compile your design in the Quartus II software to generate the output netlist files. The Quartus II software places the files in a tool-specific directory. 3. Source the Quartus II-generated Tcl Script File to set up the PrimeTime environment ...
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... Quartus II software Using the Mentor Graphics Tau software with the Quartus II software Formal Verification The Quartus II software allows you to use formal verification EDA tools to verify the logical equivalence between source design files and Quartus II output files. Figure 3 114 ■ ...
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... Verilog Output Files (.vo) (Cadence Encounter Conformal Only) The type of formal verification supported by the Quartus II software is equivalence checking, which compares the functional equivalence of the source design with the revised design by using mathematical techniques rather than by performing simulation using test vectors. Equivalence checking greatly decreases the time to verify the design ...
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... Cadence Encounter Conformal Only) Using the Cadence Encounter Conformal Software You can use the Cadence Encounter Conformal software to perform formal verification on your Quartus II designs. The formal verification software determines whether or not the Quartus II software correctly interprets the logic in the Verilog Quartus Mapping file or the source VHDL or Verilog HDL design file during synthesis and fitting ...
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... What’s in Chapter 9: Installing the Quartus II Software Getting Technical Support Getting Online Help Starting the Quartus II Interactive Tutorial Other Altera Literature Chapter System Requirements, Licensing & Technical 118 119 121 122 124 Nine Support ...
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... Quartus II software 118 ■ I NTRODUCTION TO THE , L & ICENSING ECHNICAL Refer To Altera Software Installation and Licensing manual on the Altera website Altera Complete Design Suite readme.txt file Quartus II Software Release Notes on the Altera website Quartus II Device Support Release Notes on the Altera website UARTUS ...
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... General information about Quartus II licensing Getting Technical Support The easiest way to get technical support is to use the mySupport website and register for a myAltera account and user name. Your copy of the Quartus II software is registered at the time of purchase; however, in order to use the A C LTERA ...
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... Altera website features, such as the Download Center, Self Service Licensing Center, Altera Technical Training online class registration, or Buy On-Line-Altera eStore features. To register for a myAltera account user name and password, follow these steps the mySupport website: ...
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... The mySupport website allows you to submit, view, and update technical support service requests. (800) 800-EPLD (7:00 a.m. to 5:00 p.m. Pacific time, M–F) You will need your 6-digit Altera ID to access the hotline. (408) 544-8767 (7:00 a.m. to 5:00 p.m. Pacific time, M–F) Refer To “ ...
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... NTERACTIVE Starting the Quartus II Interactive Tutorial The Quartus II software includes the Flash-based Quartus II Interactive Tutorial. The modules of this tutorial teach you how to use the basic features of the Quartus II design software, including design entry, compilation, timing analysis, programming, incremental compilation, and the SignalTap II Logic Analyzer ...
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... UARTUS NTERACTIVE UTORIAL Where to Find It The Altera website The Altera website The Altera website In Quartus II subscription packages and on the Altera website On the Altera Complete Design Suite DVD and installed with the Quartus II software The Altera website II S ■ 123 UARTUS OFTWARE ...
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... Synthesis, simulation, and verification guidelines ■ Product updates and notifications The literature that is available from the Altera website is the most current information about Altera products and features updated frequently, even after a product has been released. Altera continues to add new literature in order to provide more information on the latest features of Altera tools and devices, and to provide additional information that Altera customers have requested ...
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... Documentation Conventions The Introduction to the Quartus II Software manual uses the following conventions to make it easy for you to find and interpret information. Typographic Conventions Quartus II documentation uses the typographic conventions shown in the following table: Visual Cue Meaning Bold Initial Command names; dialog box, page, and tab titles; and button names Capitals are shown in bold, with initial capital letters ...
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... Indicates that you need to position the mouse pointer, without clicking appropriate location on the screen, such as a menu or submenu. For example: On the Help menu, point to Altera on the Web, and then click Quartus II Service Request. turn on/turn off Indicates that you must click a check box to turn a function on or off ...
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... Copyright © 2010 Altera Corporation. All rights reserved. Altera, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corpora- tion in the U.S. and other countries. ModelSim is a registered trademark of Mentor Graphics Corporation. All other product or service names are the property of their respective holders ...