SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 5

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

T
Chapter 4: Place and Route.......................................................................................................... 51
Chapter 5: Timing Analysis and Design Optimization ........................................................... 65
Chapter 6: Programming & Configuration ............................................................................... 83
Chapter 7: Debugging and Engineering Change Managment ............................................... 89
IV
ABLE OF
■
Introduction..................................................................................................................... 52
Using Incremental Compilation ................................................................................... 53
Analyzing Fitting Results .............................................................................................. 54
Optimizing the Fit .......................................................................................................... 58
Introduction..................................................................................................................... 66
Running the TimeQuest Timing Analyzer.................................................................. 66
Timing Closure................................................................................................................ 73
Introduction..................................................................................................................... 84
Creating and Using Programming Files...................................................................... 85
Introduction..................................................................................................................... 90
Using the SignalTap II Logic Analyzer........................................................................ 91
Using an External Logic Analyzer ............................................................................... 93
C
I
NTRODUCTION TO THE
ONTENTS
The RTL Viewer ................................................................................................ 45
The State Machine Viewer .............................................................................. 47
The Technology Map Viewer.......................................................................... 48
Using the Messages Window to View Fitting Results ................................ 55
Using the Report Window or Report File to View Fitting Results............ 56
Using the Chip Planner to Analyze Results ................................................. 56
Using the Design Assistant to Check Design Reliability............................ 58
Using Location Assignments.......................................................................... 58
Setting Options that Control Place & Route................................................. 59
Using the Resource Optimization Advisor .................................................. 60
Using the Design Space Explorer................................................................... 63
Viewing Timing Information for a Path........................................................ 70
Viewing Timing Delays with the Technology Map Viewer ....................... 72
Using the Chip Planner ................................................................................... 74
Using the Timing Optimization Advisor...................................................... 75
Using Netlist Optimizations to Achieve Timing Closure........................... 75
Using LogicLock Regions to Preserve Timing ............................................. 77
Using the Design Space Explorer to Achieve Timing Closure .................. 78
Power Analysis with the PowerPlay Power Analyzer ............................... 78
PowerPlay Early Power Estimator Spreadsheets ........................................ 80
Analyzing SignalTap II Data........................................................................... 92
Setting Fitter Options ........................................................................ 59
Setting Physical Synthesis Optimization Options ........................ 59
Setting Individual Logic Options that Affect Fitting.................... 60
Specifying Timing Constraints......................................................... 68
Chip Planner Tasks And Layers ...................................................... 74
Making Assignments......................................................................... 74
Q
UARTUS
II S
OFTWARE
A
LTERA
C
ORPORATION