CY3125R62 Cypress Semiconductor Corp, CY3125R62 Datasheet

CY3125R62

Manufacturer Part Number

CY3125R62

Description

TOOL DEVELOPMENT CPLD FOR UNIX

Manufacturer

Cypress Semiconductor Corp

Type

Compilerr

Datasheet

1.CY3125R62.pdf (8 pages)

Specifications of CY3125R62

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Other names

428-1302

Current page: 1 of 8
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Cypress Semiconductor Corporation

Document #: 38-03046 Rev. *A

Features

• VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364)

• IEEE Standard 1076 and 1164 VHDL synthesis

• IEEE Standard 1364 Verilog synthesis supports:

• Several design entry methods support high-level and

• UltraGen™ Synthesis and Fitting Technology:

• Supports for the following Cypress Programmable

high-level language compilers with the following

features:

supports:

low-level design descriptions:

Logic Devices:

— Designs are portable across multiple devices

— Facilitates the use of industry-standard simulation

— Support for functions and libraries facilitating

— Enumerated types

— Operator overloading

— For... Generate statements

— Integers

— Reduction and conditional operators

— Blocking and non-blocking procedural assignments

— While loops

— Integers

— Behavioral VHDL and Verilog (IF...THEN...ELSE;

— Boolean

— Structural Verilog and VHDL

— Designs can include multiple entry methods (but

— Infers “modules” such as adders, comparators, etc.,

— User-selectable speed and/or area optimization on a

— Perfect communication between synthesis and fit-

— Automatic selection of optimal flip-flop type

— Automatic pin assignment

— PSI™ (Programmable Serial Interface™)

— Delta39K™ CPLDs

— Quantum38K™ CPLDs

— Ultra37000™ CPLDs

— F

— MAX340™ CPLDs

and/or EDA environments

and synthesis tools for board and system-level

design

modular design methodology

CASE...)

only one HDL language) in a single design.

from behavioral descriptions and replaces them with

circuits pre-optimized for the target device.

block-by-block basis

ting

(D type/T type)

LASH

370i™ CPLDs

Warp

•

3901 North First Street

CPLD Development Tool for UNIX

Functional Description

Warp

Cypress’s Complex Programmable Logic Devices (CPLDs).

Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE

1364 Verilog as its Hardware Description Languages (HDL) for

design entry. Then, it synthesizes and optimizes the entered

design, and outputs a JEDEC or Intel hex file for the desired

PLD or CPLD (see Figure 1). Furthermore, Warp accepts

VHDL or Verilog produced by the Active-HDL FSM graphical

Finite State Machine editor. For simulation, Warp provides a

timing simulator, as well as VHDL and Verilog timing models

for use with third party simulators.

• VHDL and Verilog timing model output for use with

• Static Timing Report:

• Architecture Explorer and Dynamic Timing Analysis for

• Workstation support for Sun Solaris™

• On-line documentation and help

third-party simulators

PSI, Delta39K and Quantum38K devices:

— Industry-standard PLDs (16V8, 20V8, 22V10)

— Provides timing information for any path broken

— Graphical representation of exactly how your design

— Zoom from the device level down to the macrocell

— Determine the timing for any path and view that path

down by the different steps of the path

will be implemented on your specific target device

level

on a graphical representation of the chip

•

is a state-of-the-art HDL compiler for designing with

San Jose

Figure 1. Warp

Programming

File

VHDL

•

CA 95134

VHDL Design Flow

Verilog

UltraGen

Synthesis

Simulator

Fitting

Timing

and

Revised January 9, 2002

•

CY3125

State Machine

408-943-2600

Simulation Models

VHDL, Verilog

&Third-Party

Related parts for CY3125R62

CY3125R62 Summary of contents

Page 1

... Quantum38K™ CPLDs — Ultra37000™ CPLDs — F 370i™ CPLDs LASH — MAX340™ CPLDs Cypress Semiconductor Corporation Document #: 38-03046 Rev. *A ® Warp CPLD Development Tool for UNIX — Industry-standard PLDs (16V8, 20V8, 22V10) • VHDL and Verilog timing model output for use with third-party simulators • ...

Page 2

VHDL and Verilog Compilers VHDL and Verilog are powerful, industry standard languages for behavioral design entry and simulation, and are supported by all major vendors of EDA tools. They allow designers to learn a single language that is useful for ...

Page 3

IF (nickel = ’1’) THEN drinkStatus <= ten; ELSIF (dime = ’1’) THEN drinkStatus <= fifteen; ELSIF (quarter = ’1’) THEN giveDrink <= ’1’; drinkStatus <= zero END IF; -- Several states are omitted in this -- example. The omitted ...

Page 4

Figure 2. One-Bit Half Adder LIBRARY ieee; USE ieee.std_logic_1164.all; --entity declaration ENTITY half_adder IS PORT ( std_logic; sum, carry : OUT std_logic); END half_adder; --architecture body ARCHITECTURE behave OF half_adder IS BEGIN sum <= x ...

Page 5

BEGIN giveDrink = 0; returnDime = 0; returnNickel = 0; CASE(drinkStatus) zero: BEGIN IF (nickel) drinkStatus = five; ELSE IF (dime) drinkStatus = ten; ELSE IF (quarter) drinkStatus = twentyfive; END five: BEGIN IF (nickel) drinkStatus = ten; ELSE IF ...

Page 6

... The JEDEC and Intel hex files produced by Warp can also be used with any qualified third party programmer to program Cy- press CPLDs. For more information on Cypress’s ISR software see the ISR Programming Kit (CY3900i) data sheet. CY3125 370i, Ultra37000, Quantum38K, Delta39K, ...

Page 7

... CD-ROM drive • Solaris 2.5 or later Product Ordering Information Product Code Description CY3125R62 Warp development system for UNIX Warp Enterprise, UltraGen, Ultra37000, Quantum38K, Delta39K, PSI, Programmable Serial Interface, MAX340, ISR, In-System Reprogrammable, and F 370i are trademarks of Cypress Semiconductor Corporation. LASH Warp is a registered trademark of Cypress Semiconductor Corporation ...

Page 8

Document Title: CY3125 Warp® CPLD Development Tool for UNIX Document Number: 38-03046 Issue REV. ECN NO. Date ** 109903 09/22/01 *A 111243 01/22/02 Document #: 38-03046 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-01033 ...

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