CDP68HC68T1M2 Intersil, CDP68HC68T1M2 Datasheet
CDP68HC68T1M2
Specifications of CDP68HC68T1M2
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CDP68HC68T1M2 Summary of contents
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... POR PSE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Copyright Harris Corporation 1997. Copyright Intersil Americas Inc. 2001, 2004-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CDP68HC68T1 FN1547.8 Pin When Power Fails ...
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... CDP68HC68T1M2* HC68T1M2 CDP68HC68T1M2Z* (Note) HC68T1M2Z *Add “96” suffix for tape and reel. Please refer to TB347 for details on reel specifications. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. ...
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... Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature (Plastic +150°C Maximum Storage Temperature Range (T Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. ...
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Static Electrical Specifications PARAMETER Operating Current (Note 5V Crystal Operation Standby Current (Note 2.2V B Crystal Operation Input Capacitance Maximum Rise and Fall Times (Except XTAL Input and POR ...
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Functional Block Diagram CE LINE 50/60Hz XTAL IN OSCILLATOR PRESCALE XTAL OUT V BATT PRESCALE SELECT CLOCK OUT CONTROL REGISTER INT CLOCK AND V INTERRUPT DD INT CONTROL LOGIC V SS REGISTER LINE V POWER SYS INT STATUS SENSE REGISTER ...
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RAM LOCATIONS 31 32 CLOCK/CALENDAR BYTES UNUSED 63 85 TEST MODE R = READABLE W = WRITABLE TABLE 1. CLOCK/CALENDAR AND ALARM DATA MODES ADDRESS LOCATION (H) FUNCTION 20 Seconds 21 Minutes 22 Hours 12 ...
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Programmers Model - Clock Registers HEX ADDRESS RAM DATA BYTE NOTE Don’t care writes when read. 7 CDP68HC68T1 WRITE/READ REGISTERS DB7 DB0 ...
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Functional Description The SPI real-time clock consists of a clock/calendar and a 32x8 RAM. Communications is established via the SPI (Serial Peripheral Interface) bus. In addition to the clock/calendar data from seconds to years, and system flexibility provided by the ...
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FROM SYSTEM TO SYSTEM POWER POWER CONTROL V PSE SYS I CLK INTERRUPT OUT CONTROL REGISTER CPUR MISO SERIAL MOSI INTERFACE REAL-TIME CLOCK CDP68HC68T1 FIGURE 4. POWER-DOWN FUNCTIONAL DIAGRAM Power Sensing (See Figure 3) When Power Sensing ...
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The second condition that releases Power-Down occurs when the level on the V pin rises about 1.0V above SYS the level at the V input, after previously falling to the BATT level of V (see Figure 6) in the ...
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XTAL IN 22M T1 XTAL OUT C2 NOTES: 7. All frequencies recommended oscillator circuit. C crystal dependent used for 32KHz operation only. 100k to 300k range as specified by crystal manufacturer. FIGURE 7. OSCILLATOR CIRCUIT V SYS ...
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Alarm The output of the alarm comparator is enabled when this bit is set high. When a comparison occurs between the seconds, minutes and hours time and alarm counters, the interrupt output is activated. When loading the time counters, this ...
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STATUS REGISTER (Read Only) - Address 30H WATCHDOG MODE DISABLE RESET WRITE READ NOTES: 9. When interfacing to CDP68HC05 microcontrollers, serial clock phase bit, CPHA, must be set = 1 in the microcomputer’s Control Register. 10. MISO ...
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Functional Description The Serial Peripheral Interface (SPI) utilized by the CDP68HC68T1 is a serial synchronous bus for address and data transfers. The clock, which is generated by the microcomputer is active only during address and data transfers. In systems using ...
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Read/Write Data (See Figure 10) Read/Write data follows the Address/Control byte. BIT CE SCK (NOTE) MOSI D7 MISO D7 NOTE: SCK can be either polarity. FIGURE 10. READ/WRITE DATA TRANSFER WAVEFORMS Watchdog Reset (See Figure 11) When watchdog operation is ...
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CE SCK WRITE MOSI ADDRESS BYTE MOSI ADDRESS BYTE READ MISO FIGURE 12. SINGLE-BYTE TRANSFER WAVEFORMS CE SCK WRITE MOSI ADDRESS BYTE MOSI ADDRESS BYTE READ MISO DATA BYTE W/R ADDRESS DATA BYTE +1 DATA BYTE + (n-1) FIGURE 13. ...
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Timing Diagrams 5 MOSI A6 W SCK 4 5 W/R MOSI MISO CE I SCK 4 System Diagrams AC BRIDGE LINE REGULATOR NOTE: Example of a system in which power is always on. Clock circuit driven by line ...
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System Diagrams (Continued) AC LINE NOTE: Example of a system in which the power is controlled by an external source. The LINE input pin can sense when the switch opens by use of the POWER-SENSE INTERRUPT. The CDP68HC68T1 crystal drives ...
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System Diagrams (Continued) AC REGULATOR LINE 0.1 R CHARGE 0.047 1k 20k RTC V DD FIGURE 18. EXAMPLE OF A SYSTEM WITH A BATTERY BACKUP 19 CDP68HC68T1 NC 100k POR SYS V BATT PSE XTAL CPUR V ...
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System Diagrams (Continued) CLOCK BUTTON IGNITION 5V REG + 12V - LINE V BATT POR XTAL 2MHz Example of an automotive system. The V external switch is included to activate the system without turning on the ignition. Also, the CMOS ...
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Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...
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Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...