ISL95311 Intersil Corporation, ISL95311 Datasheet
ISL95311
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ISL95311 Summary of contents
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... Data Sheet Terminal Voltage 0V to 13.2V, 128 Taps I Interface The Intersil ISL95311 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The 2 wiper position is controlled interface. The potentiometer is implemented by a resistor array composed of 127 resistive elements and a wiper switching network ...
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... SIMPLE BLOCK DIAGRAM Pin Descriptions PIN NUMBER SYMBOL 1 SDA 2 GND 3 VCC SCL 2 ISL95311 7-BIT SDA WIPER REGISTER SCL (VOLATILE 7-BIT NONVOLATILE R MEMORY W R DECODER L STORE AND RECALL CONTROL CIRCUITRY A1 SLAVE ADDRESS A0 DECODE ...
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... RESISTOR MODE (Measurements between R RINL Integral non-linearity (Note 11) RDNL Differential non-linearity (Note 10) Roffset Offset (Note 9) TC Resistance Temperature Coefficient R (Note 12, 13) 3 ISL95311 Recommended Operating Conditions Temperature Range (Industrial .-40°C to +85° 2.7V to 5.5V CC +0. 8.0V to 13.2V CC Wiper current of DCP ±3.0mA TEST CONDITIONS W option U option ...
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... Clock LOW time LOW t Clock HIGH time HIGH t START condition setup time SU:STA t START condition hold time HD:STA 4 ISL95311 TEST CONDITIONS 2 = 400kHz; SDA = Open; (for I C, active, SCL read, and volatile write states only 400kHz; SDA = Open; (for I C, active, SCL ...
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... TIMING) A0, A1 Pin Timing START SCL SDA IN A0 ISL95311 TEST CONDITIONS From SDA exiting the 30 window, to SCL rising edge crossing 30 From SCL rising edge crossing 30 SDA entering the 30 From SCL rising edge crossing 70 SDA rising edge crossing 30 From SDA rising edge to SCL falling edge ...
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... C serial bus. , and with the Principles of Operation The ISL95311 is an integrated circuit incorporating one DCP with their associated register, non-volatile memory, and serial interface providing direct communication between a host and the potentiometers and memory. The resistor array is comprised of 127 individual resistors connected in series ...
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... Data states on the SDA line can change only during SCL 2 LOW periods. SDA state changes during SCL HIGH are C interface reserved for indicating START and STOP conditions (See Figure 1). On power-up of the ISL95311 the SDA pin is in the input mode. TABLE 1. MEMORY MAP NON-VOLATILE VOLATILE ...
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... Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition (See Figure 3). After each of the three bytes, the ISL95311 responds with an ACK. At this time, if the Data Byte written only to volatile registers, then the device enters its standby state. If the Data Byte written also to non-volatile memory, the ISL95311 begins its internal write cycle to non-volatile memory ...
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... FIGURE 1. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER START FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS FROM THE ISL95311 S SIGNALS T FROM THE A IDENTIFICATION MASTER R BYTE WITH T R/W=0 0 ...
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... Communicating with the ISL95311 There are 3 register addresses in the ISL95311, of which two can be used. Address 00h and address 02h are used to control the device. Address 01h is reserved and should not be used. Address 00h contains the nonvolatile Initial Value Register (IVR), and the volatile Wiper Register (WR). ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 ISL95311 10 Lead MSOP, Package Code 0.0106 [0.27] 4 ...