MC88915T Motorola Semiconductor Products, MC88915T Datasheet
MC88915T
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MC88915T Summary of contents
Page 1
... The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the MC88915T to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Multiple 88915’ ...
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PIN SUMMARY 2 Pinout: 28–Lead PLCC (Top View) FN SUFFIX PLASTIC PLCC CASE 776–02 MOTOROLA ...
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... Figure 1. MC88915T Block Diagram (All Versions) MOTOROLA 3 ...
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... MC88915TFN55 and MC88915TFN70 SYNC INPUT TIMING REQUIREMENTS Symbol t ,SYNC Inputs Rise/Fall Time, SYNC Inputs RISE/FALL From 0 SYNC Inputs Input Clock Period SYNC Inputs CYCLE Duty Cycle SYNC Inputs Input Duty Cycle SYNC Inputs 1. These t minimum values are valid when ‘Q’ output is fed back and connected to the FEEDBACK pin. This is the configuration shown in CYCLE Figure 5b ...
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... MC88915TFN55 and MC88915TFN70 FREQUENCY SPECIFICATIONS (T =– + Symbol 1 f Maximum Operating Frequency (2X_Q Output) max Maximum Operating Frequency (Q0–Q4,Q5 Output) 1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50 terminated CHARACTERISTICS (T =– ...
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... Maximum Operating Frequency (2X_Q Output) max Maximum Operating Frequency (Q0–Q4,Q5 Output) 1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50 terminated MC88915TFN100 Parameter (Voltages Referenced to GND) T =– + Test Conditions – ...
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... FEEDBACK pin 0. The minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached. PZL PHZ PLZ MOTOROLA MC88915TFN100 (continued) = 5.0V 5%, Load = 50 Terminated Min 1 0 0.5t – ...
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... Maximum Operating Frequency (2X_Q Output) max Maximum Operating Frequency (Q0–Q4,Q5 Output) 1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50 terminated MC88915TFN133 Parameter (Voltages Referenced to GND) T =– + Test Conditions – ...
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... FEEDBACK pin 0. The minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached. PZL PHZ PLZ MOTOROLA MC88915TFN133 (continued) = 5.0V 5%, Load = 50 Terminated Min 1 0 0.5t – ...
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... Maximum Operating Frequency (2X_Q Output) max Maximum Operating Frequency (Q0–Q4,Q5 Output) 1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50 terminated MC88915TFN160 Parameter (Voltages Referenced to GND + Test Conditions – ...
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... FEEDBACK pin 0. The minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached. PZL PHZ PLZ MOTOROLA MC88915TFN160 (continued) = 5.0V 5%, Load = 50 Terminated Min 1 0.5 2 0.5t – ...
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... FMAX Spec)/ resistor tied to either Analog V CC shown in Figure 2 is required to ensure no jitter is present on the MC88915T outputs. This technique causes a phase offset between the SYNC input and the output connected to the FEEDBACK input, measured at the input pins. The t ...
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Figure 2. Depiction of the Fixed SYNC to Feedback Offset (tPD) Which is Present When The t specification guarantees that the rising edges SKEWr of outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall within ...
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Calculation of Total Output–to–Skew between multiple parts (Part–to–Part skew) By combining the t specification and the information in PD Note 5, the worst case output–to–output skew between multiple 88915’s connected in parallel can be calculated. This calculation assumes that ...
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... Table 1, even though the LOCK pin may be LOW at frequencies below 10MHZ. The exact minimum frequency where the lock indicator functionality can be guaranteed will be available when the MC88915T reaches ‘MC’ status. 15 ...
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... Figure 4. Output/Input Switching Waveforms and Timing Diagrams (These waveforms represent the hook–up configuration of Figure 5a on page 17) Timing Notes: The MC88915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle. All skew specs are measured between the V are specified as ‘ ...
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Figure 5a. Wiring Diagram and Frequency Relationships With Q/2 Output Feed Back Figure 5b. Wiring Diagram and Frequency Relationships With Q4 Output Feed Back Figure 5c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feed Back MOTOROLA 17 ...
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... Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88915T Notes Concerning Loop Filter and Board Layout Issues 1. Figure 6 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter–free operation: 1a ...
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... MC88915T System Level Testing Functionality 3–state functionality has been added to the 100MHz version of the MC88915T to ease system board testing. Bringing the OE/RST pin low will put all outputs (except for LOCK) into the high impedance state. As long as the PLL_EN pin is low, the Q0– ...
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OUTLINE DIMENSIONS FN SUFFIX PLASTIC PACKAGE CASE 776–02 ISSUE BRK –M– VIEW D– –T– VIEW S VIEW ...
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... JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 Technical Information Center: 1–800–521–6274 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA are registered trademarks of Motorola, Inc. Motorola, Inc Equal MC88915T/D 21 ...