MPC870 FREESCALE [Freescale Semiconductor, Inc], MPC870 Datasheet

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... Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC875/MPC870. The CPU on the MPC875/MPC870 is a 32-bit PowerPC™ core that incorporates memory management units (MMUs) and instruction and data caches and that implements the PowerPC instruction set. This ...

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... Features Table 1 shows the functionality supported by the members of the MPC875/MPC870. Part I Cache MPC875 8 Kbyte MPC870 8 Kbyte 2 Features The MPC875/870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC875/870 features: • ...

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... Integrated controller managing crypto-execution units – Buffer size of 256 bytes for each execution unit, with flow control for large data sizes • Interrupts — Six external interrupt request (IRQ) lines MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Features 3 ...

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... USB 2.0 full-/low-speed compatible — The USB function mode has the following features: – Four independent endpoints support control, bulk, interrupt, and isochronous data transfers. MPC875/MPC870 Hardware Specifications, Rev. 3.0 4 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE , GRACEFUL STOP TRANSMIT ...

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... Can be internally connected to two serial channels (one SCC and one SMC) • PCMCIA interface — Master (socket) interface, release 2.1-compliant — Supports one independent PCMCIA socket on the MPC875/MPC870 — 8 memory or I/O windows supported • Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data — ...

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... Load/Store Bus Fast Ethernet Controller DMAs DMAs DMAs FIFOs 10/100 BaseT Media Access Control Parallel Interface Port MIII/RMII MPC875/MPC870 Hardware Specifications, Rev. 3.0 6 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figure 1. 8-Kbyte Unified Bus 32-Entry ITLB 8-Kbyte Data Cache Data MMU 32-Entry DTLB Slave/Master IF ...

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... The MPC870 block diagram is shown in Instruction Bus Instruction Cache Instruction MMU Embedded MPC8xx Processor Core Load/Store Bus Fast Ethernet Controller DMAs DMAs FIFOs 10/100 BaseT Media Access Control Parallel Interface Port MIII / RMII 3 Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC875/870. ...

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... Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or V MPC875/MPC870 Hardware Specifications, Rev. 3.0 8 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Table 2 ...

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... The modes are 1:1, where CPU and bus speeds are equal, and 2:1, where CPU frequency is twice bus speed. Die Revision 0 1 Typical power dissipation is measured at V MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Environment Single-layer board (1s) Four-layer board (2s2p) ...

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... The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], PE(14:31), TDI, TDO, TCK, TRST, TMS, MII1_TXEN, MII_MDIO are 5-V tolerant. The minimum voltage is still 2 (max) for the I C interface is 0.8 V rather than the 1 specified in the I IL MPC875/MPC870 Hardware Specifications, Rev. 3.0 10 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE = V = 1.9 V, and 3.5 V. DDL DDSYN ...

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... This thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most packages, a better model is required. MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE × ...

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... A small amount of epoxy is placed over the thermocouple junction and over about wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. MPC875/MPC870 Hardware Specifications, Rev. 3.0 12 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE ...

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... The MUR420 Schottky diodes control the maximum potential difference between the external bus and core power supplies on power up, and the 1N5820 diodes regulate the maximum potential difference on power down. MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE ...

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... PAPAR (Port A pin assignment register) PADIR (Port A data direction register) PBPAR (Port B pin assignment register) PBDIR (Port B data direction register) PCPAR (Port C pin assignment register) MPC875/MPC870 Hardware Specifications, Rev. 3.0 14 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE V V DDH DDL MUR420 1N5820 Value Field ...

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... Table 8. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode) Part Frequency Core frequency Bus frequency MPC875/MPC870 Hardware Specifications, Rev. 3.0 15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE and GND should be kept to less than half an inch per capacitor lead and GND planes should be used ...

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... B1) B7a CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR output hold (MIN = 0.25 B7b CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2) IWP(0:2), LWP(0:1), STS output × hold (MIN = 0.25 B1) MPC875/MPC870 Hardware Specifications, Rev. 3.0 16 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 66 MHz Min Max 40 66.67 20 33.33 Table 10. Bus Operation Timings 33 MHz ...

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... BB, BG, BR, valid to CLKOUT (setup time) × 2 (4MIN = 0. 0.00) B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid (hold time) (MIN = 0.00 B17a CLKOUT to KR, RETRY, CR valid (hold × time) (MIN = 0. 2.00) MPC875/MPC870 Hardware Specifications, Rev. 3.0 17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 33 MHz Min Max Min — 13.80 — — 13.80 — ...

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... B1 + 9.00) B27 A(0:31) and BADDR(28:30 asserted GPCM ACS = 10, TRLX = 1 × (MIN = 1.25 B1 – 2.00) B27a A(0:31) and BADDR(28:30 asserted GPCM ACS = 11, TRLX = 1 × (MIN = 1.50 B1 – 2.00) MPC875/MPC870 Hardware Specifications, Rev. 3.0 18 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 33 MHz 40 MHz Min Max Min 6.00 — 6.00 × 6.00) 1.00 — ...

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... High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0 × (MIN = 1.50 B1 – 2.00) B29e CS negated to D(0:31) High-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 × (MIN = 1.50 B1 – 2.00) MPC875/MPC870 Hardware Specifications, Rev. 3.0 19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 33 MHz Min Max Min — 9.00 — 7.60 14.30 6.30 13.00 3.80 10.50 3.13 — ...

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... ACS == 11, EBDF = 1 × (MIN = 0.375 B1 – 3.00) B30d WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) invalid GPCM write access TRLX = 1, CSNT =1, CS negated to A(0:31) invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or 11, EBDF = 1 MPC875/MPC870 Hardware Specifications, Rev. 3.0 20 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 33 MHz 40 MHz Min Max Min 5.00 — ...

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... UPM, EBDF = 1 × (MAX = 0.375 B1 + 6.60) B33 CLKOUT falling edge to GPL valid, as requested by control bit GxT4 in the corresponding word in the UPM × (MAX = 0. 6.00) MPC875/MPC870 Hardware Specifications, Rev. 3.0 21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 33 MHz 40 MHz 66 MHz Min Max Min Max Min Max 1 ...

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... AS valid to CLKOUT rising edge × (MIN = 0. 7.00) B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid to CLKOUT rising edge × (MIN = 0. 7.00) B41 TS valid to CLKOUT rising edge (setup × time) (MIN = 0. 7.00) MPC875/MPC870 Hardware Specifications, Rev. 3.0 22 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 33 MHz 40 MHz Min Max Min Max 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 5.60 — 4.30 — 13.20 — ...

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... B37 and B38 are specified to enable the freeze of the UPM output signals as described in 9 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 22. MPC875/MPC870 Hardware Specifications, Rev. 3.0 23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 33 MHz 40 MHz 66 MHz ...

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... Inputs A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification Figure 5 provides the timing for the external clock. CLKOUT MPC875/MPC870 Hardware Specifications, Rev. 3.0 24 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 0 2.0 V 2.0 V 0 ...

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... Figure 6. Synchronous Output Signals Timing Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT TS, BB TA, BI TEA Figure 7. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MPC875/MPC870 Hardware Specifications, Rev. 3.0 25 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE B8 B9 B8a B9 B8b ...

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... Figure 8. Synchronous Input Signals Timing Figure 9 provides normal case timing for input data. It also applies to normal read accesses under the control of the user-programmable machine (UPM) in the memory controller. CLKOUT TA D[0:31] MPC875/MPC870 Hardware Specifications, Rev. 3.0 26 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE B16 B17 B16a B17a ...

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... Figure 14 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT TS A[0:31] CSx OE WE[0:3] D[0:31] Figure 11. External Bus Read Timing (GPCM Controlled—ACS = 00) MPC875/MPC870 Hardware Specifications, Rev. 3.0 27 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE B20 B21 B11 B12 B8 B22 B25 B28 B18 ...

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... CLKOUT TS A[0:31] CSx OE D[0:31] Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT TS A[0:31] CSx OE D[0:31] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MPC875/MPC870 Hardware Specifications, Rev. 3.0 28 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE B11 B12 B8 B22a B24 B25 B18 B11 B12 B8 B22b B22c ...

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... Bus Signal Timing CLKOUT B11 TS A[0:31] CSx OE D[0:31] Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11) MPC875/MPC870 Hardware Specifications, Rev. 3.0 29 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE B12 B8 B22a B27 B27a B18 B22b B22c B23 B26 B19 Freescale Semiconductor ...

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... Figure 17 provide the timing for the external bus write controlled by various GPCM factors. CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0) MPC875/MPC870 Hardware Specifications, Rev. 3.0 30 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE B11 B12 B8 B22 B25 B26 B8 B30 B23 ...

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... Bus Signal Timing CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) MPC875/MPC870 Hardware Specifications, Rev. 3.0 31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE B11 B12 B8 B22 B28b B28d B25 B26 B28a B28c B8 B30a B30c B23 B29c B29g B29a B29f B9 Freescale Semiconductor ...

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... Bus Signal Timing CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) MPC875/MPC870 Hardware Specifications, Rev. 3.0 32 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE B12 B8 B22 B28b B28d B25 B26 B8 B28a B28c B30b B30d B23 B29e B29i B29d B29h B29b B9 Freescale Semiconductor ...

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... Figure 18 provides the timing for the external bus controlled by the UPM. CLKOUT B8 A[0:31] CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 18. External Bus Timing (UPM Controlled Signals) MPC875/MPC870 Hardware Specifications, Rev. 3.0 33 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE B31a B31d B31 B34 B34a B34b B32a B32d B32 ...

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... UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 20. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC875/MPC870 Hardware Specifications, Rev. 3.0 34 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE B38 B38 Freescale Semiconductor ...

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... Figure 22. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00) Figure 23 provides the timing for the asynchronous external master control signals negation. AS CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 23. Asynchronous External Master—Control Signals Negation Timing MPC875/MPC870 Hardware Specifications, Rev. 3.0 35 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE B41 B42 B40 B39 B40 ...

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... Figure 24. Interrupt Detection Timing for External Level Sensitive Lines Figure 25 provides the interrupt detection timing for the external edge-sensitive lines. CLKOUT IRQx Figure 25. Interrupt Detection Timing for External Edge-Sensitive Lines MPC875/MPC870 Hardware Specifications, Rev. 3.0 36 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Table 11. Interrupt Timing 1 Characteristic ...

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... These synchronous timings define when the WAITA signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITA assertion will be effective only detected 2 cycles before the PSL timer expiration. See Chapter 16, “PCMCIA Interface,” in the MPC885 PowerQUICC Family User’s Manual. MPC875/MPC870 Hardware Specifications, Rev. 3.0 37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Table 12 ...

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... PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 26. PCMCIA Access Cycles Timing External Bus Read MPC875/MPC870 Hardware Specifications, Rev. 3.0 38 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE P44 P46 P45 P48 P50 P52 P53 ...

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... PCWE, IOWR ALE D[0:31] Figure 27. PCMCIA Access Cycles Timing External Bus Write Figure 28 provides the PCMCIA WAIT signals detection timing. CLKOUT WAITA Figure 28. PCMCIA WAIT Signals Detection Timing MPC875/MPC870 Hardware Specifications, Rev. 3.0 39 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE P44 P46 P45 P48 P50 P52 ...

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... PCMCIA output port timing for the MPC875/870. CLKOUT Output Signals HRESET OP2, OP3 Figure 30 provides the PCMCIA input port timing for the MPC875/870. CLKOUT Input Signals MPC875/MPC870 Hardware Specifications, Rev. 3.0 40 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Table 13. PCMCIA Port Timing 33 MHz 40 MHz Min Max Min — 19.00 — ...

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... DSCK low to DSDO invalid Figure 31 provides the input timing for the debug port clock. DSCK Figure 32 provides the timing for the debug port. DSCK DSDI DSDO MPC875/MPC870 Hardware Specifications, Rev. 3.0 41 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Table 14. Debug Port Timing Characteristic D61 D62 D61 D63 Figure 31 ...

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... R80 (MIN = 3.00 × B1) DSDI, DSCK hold time R81 (MIN = 0.00 × 0.00) SRESET negated to CLKOUT R82 rising edge for DSDI and DSCK sample (MIN = 8.00 × B1) MPC875/MPC870 Hardware Specifications, Rev. 3.0 42 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Table 15. Reset Timing 33 MHz 40 MHz Min Max Min Max Min — ...

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... Figure 34 provides the reset timing for the data bus weak drive during configuration. CLKOUT HRESET RSTCONF D[0:31] (OUT) (Weak) Figure 34. Reset Timing—Data Bus Weak Drive During Configuration MPC875/MPC870 Hardware Specifications, Rev. 3.0 43 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE R71 R76 R73 R74 R75 ...

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... TCK falling edge to output valid out of high impedance J94 TCK falling edge to output high impedance J95 Boundary scan input valid to TCK rising edge J96 TCK rising edge to boundary scan input invalid MPC875/MPC870 Hardware Specifications, Rev. 3.0 44 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE R70 R82 R80 R80 ...

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... IEEE 1149.1 Electrical Specifications TCK TCK TMS, TDI TDO Figure 37. JTAG Test Access Port Timing Diagram TCK TRST MPC875/MPC870 Hardware Specifications, Rev. 3.0 45 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE J82 J83 J82 J84 Figure 36. JTAG Test Clock Input Timing J85 J86 J87 J88 ...

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... Port C interrupt pulse width low (edge-triggered mode) 36 Port C interrupt minimum time between active edges Figure 40 shows the port C interrupt detection timing. Port C (Input) MPC875/MPC870 Hardware Specifications, Rev. 3.0 46 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE J92 J93 Table 17. Port C Interrupt Timing Characteristic 35 Figure 40. Port C Interrupt Detection Timing ...

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... TA assertion to falling edge of the clock setup time (applies to external TA) 1 Applies to high-to-low mode (EDM=1) CLKO (Output) DREQ (Input) Figure 41. IDMA External Requests Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 47 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figure 41 to Table 18. IDMA Controller Timing Characteristic 1 ...

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... CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 42. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 43. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA MPC875/MPC870 Hardware Specifications, Rev. 3.0 48 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor ...

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... Num 50 BRGO rise and fall time 51 BRGO duty cycle 52 BRGO cycle 50 BRGOX Figure 45. Baud Rate Generator Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 49 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 42 Figure 45. Table 19. Baud Rate Generator Timing Characteristic ...

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... L1RCLKB, L1TCLKB width low (DSC = 0) 71a L1RCLKB, L1TCLKB width high (DSC = 0) 72 L1TXDB, L1ST1 and L1ST2, L1RQ, L1CLKO rise/fall time 73 L1RSYNCB, L1TSYNCB valid to L1CLKB edge (SYNC setup time) MPC875/MPC870 Hardware Specifications, Rev. 3.0 50 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figure Table 20. Timer Timing Characteristic 60 ...

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... Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate ns. 4 These strobes and TxD on the first bit of the frame become valid after the L1CLKB edge or L1SYNCB, whichever comes later. MPC875/MPC870 Hardware Specifications, Rev. 3.0 51 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Table 21. SI Timing (continued) ...

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... CPM Electrical Characteristics L1RCLKB (FE=0, CE=0) (Input) 71 L1RCLKB (FE=1, CE=1) (Input) L1RSYNCB (Input) 73 L1RXDB (Input) L1ST(2-1) (Output) Figure 47. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC875/MPC870 Hardware Specifications, Rev. 3.0 52 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 70 71a 72 RFSD BIT0 Freescale Semiconductor ...

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... CPM Electrical Characteristics L1RCLKB (FE=1, CE=1) (Input) 82 L1RCLKB (FE=0, CE=0) (Input) 75 L1RSYNCB (Input L1RXDB (Input) 76 L1ST(2-1) (Output) L1CLKOB (Output) Figure 48. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC875/MPC870 Hardware Specifications, Rev. 3.0 53 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 72 83a RFSD=1 77 BIT0 Freescale Semiconductor ...

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... CPM Electrical Characteristics L1TCLKB (FE=0, CE=0) (Input) 71 L1TCLKB (FE=1, CE=1) (Input) 73 L1TSYNCB (Input) L1TXDB (Output) L1ST(2-1) (Output) Figure 49. SI Transmit Timing Diagram (DSC = 0) MPC875/MPC870 Hardware Specifications, Rev. 3.0 54 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 70 72 TFSD 80a BIT0 Freescale Semiconductor ...

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... CPM Electrical Characteristics L1RCLKB (FE=0, CE=0) (Input) L1RCLKB (FE=1, CE=1) (Input) 75 L1RSYNCB (Input) 73 L1TXDB BIT0 (Output) 80 78a L1ST(2-1) (Output L1CLKOB (Output) Figure 50. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC875/MPC870 Hardware Specifications, Rev. 3.0 55 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 72 83a 82 TFSD Freescale Semiconductor ...

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... CPM Electrical Characteristics MPC875/MPC870 Hardware Specifications, Rev. 3.0 56 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figure 51. IDL Timing Freescale Semiconductor ...

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... CD3 setup time to RCLK3 rising edge 1 The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1. 2 Also applies to CD and CTS hold time when they are used as external sync signals MPC875/MPC870 Hardware Specifications, Rev. 3.0 57 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Table 22. NMSI External Clock Timing Characteristic ...

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... Figure 52. SCC NMSI Receive Timing Diagram TCLK3 102 TxD3 (Output) RTS3 (Output) CTS3 (Input) CTS3 (SYNC Input) Figure 53. SCC NMSI Transmit Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 58 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 102 101 100 107 102 101 100 103 105 ...

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... TCLK3 rise/fall time 129 TCLK3 width low 1 130 TCLK3 clock period 131 TXD3 active delay (from TCLK3 rising edge) 132 TXD3 inactive delay (from TCLK3 rising edge) MPC875/MPC870 Hardware Specifications, Rev. 3.0 59 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 102 101 100 103 104 107 105 Figure 54 ...

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... SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. CLSN(CTS1) (Input) Figure 55. Ethernet Collision Timing Diagram RCLK3 RxD3 (Input) RENA(CD3) (Input) Figure 56. Ethernet Receive Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 60 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Table 24. Ethernet Timing (continued) Characteristic 2 2 120 121 124 ...

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... SMCLK rise/fall time 153 SMTXD active delay (from SMCLK falling edge) 154 SMRXD/SMSYNC setup time 155 RXD1/SMSYNC hold time 1 SyncCLK must be at least twice as fast as SMCLK. MPC875/MPC870 Hardware Specifications, Rev. 3.0 61 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 128 121 132 Figure 58. Table 25. SMC Transparent Timing ...

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... Master data hold time (inputs) 164 Master data valid (after SCK edge) 165 Master data hold time (outputs) 166 Rise time output 167 Fall time output MPC875/MPC870 Hardware Specifications, Rev. 3.0 62 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 152 151 151 150 NOTE 154 ...

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... SPICLK (CI=1) (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI msb (Output) Figure 60. SPI Master ( Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 63 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 167 166 160 167 166 Data lsb 165 164 166 Data lsb 167 ...

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... SPICLK (CI=1) (Input) 177 SPIMISO msb (Output) 175 176 SPIMOSI msb (Input) Figure 61. SPI Slave ( Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 64 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figure 61 and Figure Table 27. SPI Slave Timing Characteristic 172 182 181 170 181 182 ...

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... High period of SCL 205 Start condition setup time 206 Start condition hold time 207 Data hold time 208 Data setup time 209 SDL/SCL rise time MPC875/MPC870 Hardware Specifications, Rev. 3.0 65 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 172 170 182 181 181 182 180 msb ...

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... SDL/SCL fall time 211 Stop condition setup time 1 SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) × pre_scalar × 2). The ratio SyncClk/(Brg_Clk/pre_scalar) must be greater than or equal to 4/1. MPC875/MPC870 Hardware Specifications, Rev. 3.0 66 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 2 C Timing (SCL < 100 KH ) (continued) Z ...

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... The receiver functions correctly MII_RX_CLK maximum frequency of 25 MHz +1%. The reduced MII (RMII) receiver functions correctly RMII_REFCLK maximum frequency of 50 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency – 1%. MPC875/MPC870 Hardware Specifications, Rev. 3.0 67 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 204 ...

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... Num M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid M7 MII_TX_CLK pulse width high M8 MII_TX_CLK pulse width low MPC875/MPC870 Hardware Specifications, Rev. 3.0 68 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Table 31. MII Receive Signal Timing Characteristic Table 32. MII Transmit Signal Timing ...

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... Table 33 provides information on the MII async inputs signal timing. Num M9 MII_CRS, MII_COL minimum pulse width Figure 66 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL MPC875/MPC870 Hardware Specifications, Rev. 3.0 69 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Characteristic Table 33. MII Async Inputs Signal Timing ...

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... M15 MII_MDC pulse width low Figure 67 shows the MII serial management channel timing diagram. MII_MDC (output) MII_MDIO (output) MII_MDIO (input) Figure 67. MII Serial Management Channel Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 70 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Characteristic M14 MM15 M10 M11 ...

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... JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the MPC885 PowerQUICC Family User’s Manual. The pin numbering starts with B2 in order to conform to the JEDEC standard for 23-mm body size using a 16 × 16 array. MPC875/MPC870 Hardware Specifications, Rev. 3.0 71 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Temperature (Tj) Frequency (MHz) 0° ...

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... R16, N14, M14, P15, P17, P16, N15, N16, M15, N17, L14, M16, L15, M17, K14, L16, L17, K17, G17, K15, J16, J15, G16, J14, H17, H16, G15, K16, H14, J17, H15, F17 TSIZ0 F16 REG MPC875/MPC870 Hardware Specifications, Rev. 3.0 72 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE ...

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... IRQ0 M6 IRQ1 P5 IRQ7 N5 CS[0:5] B14, E11, C14, B15, E13, B16 CS6 F12 CE1_B CS7 D15 CE2_B MPC875/MPC870 Hardware Specifications, Rev. 3.0 73 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE JEDEC Standard (continued) — Pin Number Type Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Output Bidirectional Active pull-up (3 ...

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... XTAL D6 EXTAL D7 CLKOUT G4 EXTCLK B4 TEXP B3 ALE_A B7 CE1_A C15 CE2_A D14 WAIT_A D4 MPC875/MPC870 Hardware Specifications, Rev. 3.0 74 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE JEDEC Standard (continued) — Pin Number Type Output Output Output Output Output Output Output Output Bidirectional (3.3 V only) Bidirectional Output Input (3.3 V only) Input (3 ...

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... PA14 U16 USBOE PA11 R9 RXD4 MII1-TXD0 RMII1-TXD0 PA10 R12 MII1-TXERR TIN4 CLK7 MPC875/MPC870 Hardware Specifications, Rev. 3.0 75 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE JEDEC Standard (continued) — Pin Number Type Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3 ...

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... SPICLK PB29 R17 SPIMOSI PB28 R14 SPIMISO BRGO4 PB27 N13 I2CSDA BRGO1 PB26 N12 I2CSCL BRGO2 MPC875/MPC870 Hardware Specifications, Rev. 3.0 76 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE JEDEC Standard (continued) — Pin Number Type Bidirectional Bidirectional Bidirectional Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) ...

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... T3 RXD4 MII-MDC RMII-MDC PE31 P9 CLK8 L1TCLKB MII1-RXCLK PE30 R8 L1RXDB MII1-RXD2 MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Mechanical Data and Ordering Information JEDEC Standard (continued) — Pin Number Type Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) ...

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... TOUT1 MII2-RXD0 RMII2-RXD0 PE20 U3 MII2-TXER PE19 R6 L1TXDB MII2-TXEN RMII2-TXEN PE18 M5 SMTXD1 MII2-TXD3 MPC875/MPC870 Hardware Specifications, Rev. 3.0 78 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE JEDEC Standard (continued) — Pin Number Type Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional ...

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... H8, H9, H10, H11, J8, J9, J10, J11, K8, K9, K10, K11, L8, L9, L10, L11, U15 V F7, F8, F9, F10, F11, H6, H13, J6, J13, K6, K13, L6, L13, N7, N8, DDL N9, N10, N11 MPC875/MPC870 Hardware Specifications, Rev. 3.0 79 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE JEDEC Standard (continued) — Pin Number Type ...

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... Mechanical Data and Ordering Information Table 36. Pin Assignments Name V G7, G8, G9, G10, G11, G12, H7, H12, J7, J12, K7, K12, L7, L12, M7, DDH M8, M9, M10, M11, M12 N/C B17, T16, U2, U17 MPC875/MPC870 Hardware Specifications, Rev. 3.0 80 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE JEDEC Standard (continued) — Pin Number Type Power No-connect ...

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... DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC875/870VRXXX. Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC875/870ZTXXX. Figure 69. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Mechanical Data and Ordering Information 81 ...

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... Released to the external web. 1.1 10/2003 Added TDMb to the MPC875 Features list, the MPC875 Block Diagram, added 13.5 Serial Interface AC Electrical Specifications, and removed TDMa from the pin descriptions. MPC875/MPC870 Hardware Specifications, Rev. 3.0 82 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Table 37. Document Revision History Changes Freescale Semiconductor ...

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... Added RMII1_EN under M1II_EN in Table 36 Pin Assignments • Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL Max of the I2C Standard • Put the new part numbers in the Ordering Information Section MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Document Revision History ...

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How to Reach Us: USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 Japan: Freescale Semiconductor Japan Ltd. Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 Asia/Pacific: Freescale Semiconductor Hong ...