P89LV51RD2 Philips Semiconductors, P89LV51RD2 Datasheet
P89LV51RD2
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P89LV51RD2 Summary of contents
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... The P89LV51RD2 is an 80C51 microcontroller with 64 kB Flash and 1024 bytes of data RAM. A key feature of the P89LV51RD2 is its X2 mode option. The design engineer can choose to run the application with the conventional 80C51 clock rate (12 clocks per machine cycle) or select the X2 mode (6 clocks per machine cycle) to achieve twice the throughput at the same clock frequency. Another way to benefi ...
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... Type number P89LV51RD2BA P89LV51RD2FA P89LV51RD2BBC P89LV51RD2BN 3.1 Ordering options Table 2: Type number P89LV51RD2BA P89LV51RD2FA P89LV51RD2BBC P89LV51RD2BN 9397 750 14101 Product data Brown-out detection Low power modes Power-down mode with external interrupt wake-up Idle mode DIP40, PLCC44 and TQFP44 packages Ordering information Package ...
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... Philips Semiconductors 4. Block diagram CRYSTAL OR RESONATOR Fig 1. P89LV51RD2 block diagram. 9397 750 14101 Product data HIGH PERFORMANCE 80C51 CPU 64 kB CODE FLASH INTERNAL 1 kB DATA RAM PORT 3 PORT 2 PORT 1 PORT 0 OSCILLATOR Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core ...
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... CEX4/SCK/P1.7 9 RST 10 11 RXD/P3 TXD/P3 INT0/P3.2 INT1/P3.3 15 T0/P3.4 16 T1/P3.5 17 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core P89LV51RD2BA P89LV51RD2FA 002aaa509 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 ALE/PROG 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2 ...
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... CEX0/P1.3 4 CEX1/SS/P1.4 5 CEX2/MOSI/P1.5 6 CEX3/MISO/P1.6 7 CEX4/SCK/P1.7 8 RST 9 RXD/P3.0 10 TXD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 002aaa507 Rev. 03 — 11 October 2004 P89LV51RD2 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 ALE/PROG 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2 ...
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... CEX3/MISO/P1.6 2 CEX4/SCK/P1.7 3 RST 4 RXD/P3 TXD/P3 INT0/P3.2 INT1/P3.3 9 T0/P3.4 10 T1/P3.5 11 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core P89LV51RD2BBC 002aaa508 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 33 P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 ALE/PROG 26 PSEN 25 P2.7/A15 24 P2.6/A14 23 P2.5/A13 ...
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... Philips Semiconductors 5.2 Pin description Table 3: P89LV51RD2 pin description Symbol Pin DIP40 TQFP44 P0.0 to 39-32 37-30 P0.7 P1.0 to 1-8 40-44, 1-3 2-9 P1 9397 750 14101 Product data Type Description PLCC44 43-36 I/O Port 0: Port 8-bit open drain bi-directional I/O port. Port 0 pins that have ‘1’s written to them float, and in this state can be used as high-impedance inputs ...
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... Philips Semiconductors Table 3: P89LV51RD2 pin description Symbol Pin DIP40 TQFP44 P2.0 to 21-28 18-25 P2.7 P3.0 to 10-17 5, 7-13 P3 PSEN 29 26 RST 9 4 9397 750 14101 Product data …continued Type Description PLCC44 24-31 I/O Port 2: Port 8-bit bi-directional I/O port with with internal internal pull-ups ...
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... Philips Semiconductors Table 3: P89LV51RD2 pin description Symbol Pin DIP40 TQFP44 ALE PROG 17, 28, 39 XTAL1 19 15 XTAL2 [1] ALE loading issue: When ALE pin experiences higher loading (>30 pF) during the reset, the microcontroller may accidentally enter into modes other than normal working mode ...
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... Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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Table 4: Special function registers * indicates SFRs that are bit addressable. Name Description Bit address ACC* Accumulator AUXR Auxiliary function register AUXR1 Auxiliary function register 1 Bit address B* B register CCAP0H Module 0 Capture HIGH CCAP1H Module 1 ...
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Table 4: Special function registers …continued * indicates SFRs that are bit addressable. Name Description FST Flash Status Register Bit address IEN0* Interrupt Enable 0 Bit address IEN1* Interrupt Enable 1 Bit address IP0* Interrupt Priority IP0H Interrupt Priority 0 ...
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Table 4: Special function registers …continued * indicates SFRs that are bit addressable. Name Description SADDR Serial Port Address Register SADEN Serial Port Address Enable Bit address SPCTL SPI Control Register SPCFG SPI Configuration Register SPDAT SPI Data SP Stack ...
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... Note that circuit is being used, provisions should be made to rise time does not exceed 1 millisecond and the oscillator start-up DD Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Table addresses above 1FFFh User code (in Block 0) © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... The POF flag will remain active until cleared by software. Following a power-on or external reset the P89LV51RD2 will force the SWR and BSEL bits (FCF[1:0]) = 00. This causes the bootblock to be mapped into the lower code memory and the device will execute the ISP code in the boot block and attempt to autobaud to the host ...
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... The data RAM has 1024 bytes of internal memory. The device can also address for external data memory. 7.1.7 Expanded data RAM addressing The P89LV51RD2 has RAM. See memory structure.” on page The device has four sections of internal data memory: 1 ...
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... When ‘1’, every MOVX @Ri/@DPTR instruction targets external data memory by default. AO ALE off: disables/enables ALE results in ALE emitted at a constant rate of is active only during a MOVX or MOVC. Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core ...
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... ADDR < 0300H RD/WR not asserted RD/WR asserted RD/WR asserted RD/WR asserted Access limited to ERAM address within 0 to 0FFH; cannot access 100H to 02FFH. Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Table 9 MOVX @Ri MOVX A, @Ri ADDR 0300H ADDR = any RD/WR asserted RD/WR not asserted © ...
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... DPTR1 is selected. Quickly switching between the two data 1 AUXR1 / bit0 DPS DPS = 0 DPTR0 DPH DPS = 1 DPTR1 83H Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core FFH (DIRECT (INDIRECT ADDRESSING) ADDRESSING) SPECIAL FUNCTION UPPER 128 BYTES REGISTERS (SFRs) INTERNAL RAM ...
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... Flash memory In-Application Programming 7.2.1 Flash organization The P89LV51RD2 program memory consists block. An In-System Programming (ISP) capability second 8 kB block, is provided to allow the user code to be programmed in-circuit through the serial port. There are three methods of erasing or programming of the Flash memory that may be used. First, the Flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point (IAP) ...
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... The operation indicated by the record type is not performed until the entire record has been received. Should an error occur in the checksum, the P89LV51RD2 will send an ‘X’ out the serial port indicating a checksum error. If the checksum calculation is found to match the checksum in the record, then the command will be executed. In most cases, successful reception of the record will be indicated by transmitting a ‘ ...
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... Where: xxxxxx = required field but value is a ‘don’t care’ checksum Example: :00000002FE Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... MSB first eeee = ending address, MSB first ff = subfunction 00 = display data 01 = blank check cc = checksum Subfunction codes: Example: :0500000400001FFF00D9 (display from 0000h to 1FFFh) Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Example: :03000008010203EF (verify s/n = 010203) Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Reset and run user code :xxxxxx0Bcc Where: xxxxxx = required field but value is a ‘don’t care’ Reset and run user code cc = checksum Example: :0000000BF5 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Return parameter(s): ACC = device data Input parameters 05h DPL = 01H = security bit DPL = 05H = Double Clock Return parameter(s): ACC = 00 = pass ACC = !00 = fail Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Return parameter(s): ACC = 00 = pass ACC = !00 = fail 1 of the oscillator frequency the oscillator frequency. There are no restrictions on the duty cycle 12 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Table 14 and Table 15). © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to Timer 0 Interrupt routine software. TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off. Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core T0GATE T0C/T T0M1 8048 timer ‘ ...
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... TRn TnGate 1 allows the Timer to be controlled by external input INTn, to facilitate pulse 1 7). The GATE bit is in the TMOD register. Figure 9. Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Figure 8 shows Mode 0 operation. overflow TLn THn (5-bits) (8-bits) control ...
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... Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, the P89LV51RD2 can look like it has an additional Timer. Note: When Timer Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator any application not requiring an interrupt ...
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... T2CON - Timer/Counter 2 control register (address C8H) bit allocation TF2 EXF2 RCLK Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core overflow TL0 TF0 (8-bits) control overflow TH0 TF1 (8-bits) control Table 19 (Table 22 and Table 23). ...
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... Reserved for future use. Should be set to ‘0’ by user programs. T2OE Timer 2 Output Enable bit. Used in programmable clock-out mode only. DCEN Down Count Enable bit. When set, this allows Timer configured as an up/down counter. Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core /6) osc /12 OSC 4 3 ...
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... RCAP2L RCAP2H control EXEN2 Table 22 and Table 23). When reset is applied, DCEN = 0 and Timer 2 shows Timer 2 counting up automatically (DCEN = 0). Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core 12. TH2 TF2 (8-bits) Timer 2 interrupt EXF2 002aaa523 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... DCEN = and Timer 2 is enabled to count up or down. This mode 1 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core TH2 TF2 (8-bits) Timer 2 interrupt EXF2 002aaa524 (C/ frequency of signal on T2 pin . ‘ ...
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... FFH C/ TL2 (8-bits) control C/ TR2 RCAP2L RCAP2H (up counting reload value) operating frequency. OscillatorFrequency 65536 RCAP2H RCAP2L Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core toggle EXF2 FFH underflow TH2 TF2 (8-bits) overflow count direction down T2EX pin 002aaa525 © ...
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... Timer 2 in baud rate generator mode: C/ control C/ TR2 transition detector EXF2 control EXEN2 OscillatorFrequency 65536 RCAP2H RCAP2L – Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Section 7.5 “UARTs” on page 37 TL2 TH2 TX/RX baud rate (8-bits) (8-bits) reload RCAP2L RCAP2H Timer 2 interrupt 002aaa526 1 6 © ...
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... Timer 2 generated commonly used baud rates Osc freq 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 6 MHz 6 MHz Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core baud rate) Timer 2 RCAP2H RCAP2L ...
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... In Mode 0, SM2 should be ‘0’. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core 1 of the CPU clock 6 1 ...
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... SCON - Serial port control register (address 98H) SM0/SM1 mode definition UART mode 0: shift register 1: 8-bit UART 2: 9-bit UART 3: 9-bit UART Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core …continued Baud rate CPU clock/6 variable CPU clock/32 or CPU clock/16 variable ...
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... The SADEN mask can be logically ANDed with 9397 750 14101 Product data 8-bit microcontrollers with 80C51 core , the receive interrupt will not be activated unless a valid 1 Rev. 03 — 11 October 2004 P89LV51RD2 1. . This feature address byte and ‘0’ in the ‘1’ will interrupt all ‘ ...
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... This device uses the methods presented in ‘Broadcast’ address has been received or not. rx_byte(7) saddr(7) rx_byte(0) saddr(0) logic used by P89LV51RD2 UART to detect 'given address' in received data saddr(7) saden(7) saddr(0) saden(0) logic used by P89LV51RD2 UART to detect 'given address' in received data Fig 16. Schemes used by the UART to detect ‘given’ and ‘broadcast’ addresses when multiprocessor communications is enabled The following examples will help to show the versatility of this scheme ...
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... SPI description The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the P89LV51RD2 and peripheral devices or between several P89LV51RD2 devices. devices. The SCK pin is the clock output and input for the master and slave modes, respectively. The SPI clock generator will start following a write to the master devices SPI data register ...
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... SPI Clock Rate Select bit 0. Along with SPR1 controls the SCK rate of the device when a master. SPR1 and SPR0 have no effect on the slave. See Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core MSB Slave LSB MISO 8-bit Shift Register ...
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... MSB MSB MSB MSB Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core SCK = f divided by osc 128 ‘0’ by user programs LSB 2 1 LSB ...
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... WDT COUNTER UPPER BYTE WDTC WDTD WDTC - Watchdog control register (address COH) bit allocation Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core 1/f CLK (XTAL1) is the oscillator osc WDT reset internal reset 002aaa531 WDOUT WDRE WDTS © ...
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... Timer 0 overflow, or the 6 2 Table 37 16 bits MODULE0 MODULE1 MODULE2 MODULE3 MODULE4 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core ‘0’ by user programs. and Table 38). P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 002aaa532 © ...
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... When a module is used in the PWM mode these registers are used to control the duty cycle of the output. 9397 750 14101 Product data 8-bit microcontrollers with 80C51 core Figure Rev. 03 — 11 October 2004 P89LV51RD2 22. Figure 22). © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Reserved for future use. Should be set to CPS1, PCA Count Pulse Select (see CPS0 ECF PCA Enable Counter Overflow Interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function. Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core CCON CCF3 CCF2 CCF1 CCF0 (D8h) IEN0 ...
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... Reserved for future use. Should be set to ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core / 6 osc / 6 osc 4 3 ...
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... Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core ECCFn Module function 0 no operation x 16-bit capture by a positive-edge trigger on CEXn x 16-bit capture by a negative-edge trigger on CEXn x 16-bit capture by any transition on CEXn x 16-bit software timer ...
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... CCF4 CCF3 CCF2 CCF1 (to CCFn) capture CAPNn MATn TOGn PWMn Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core CCON CCF0 (C0h) PCA interrupt PCA timer/counter CH CL CCAPnH CCAPnL CCAPMn ECCFn (DAH to DEH) (Figure 24) by setting both the © ...
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... CEX output (on port 1) associated with the PCA module CCF4 CCAPnH CCAPnL match 16-BIT COMPARATOR CH CL PCA timer/counter - ECOMn CAPPn CAPNn 0 0 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core CCF3 CCF2 CCF1 CCF0 (to CCFn) MATn TOGn PWMn ECCFn CCF3 CCF2 CCF1 CCF0 (to CCFn) ...
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... COMPARATOR CL CCAPnL CL PCA timer/counter CAPNn MATn TOGn PWMn Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core (Figure 26). Output frequency 0 CEXn 1 CCAPMn ECCFn (DAH to DEH) 1 Figure 26 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 002aaa541 ...
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... Note that the Vector Interrupt Address Enable 0003H EX0 004BH EBO 000BH ET0 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Interrupt Service Priority Priority PX0/H 1 (highest) PBO/H 2 PT0/H 3 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Product data …continued Vector Interrupt Address Enable 0013H EX1 001BH ET1 0033H EC 0023H ES 002BH ET2 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Interrupt Service Priority Priority PX1/H 4 PT1/H 5 PPCH 6 PS/H 7 PT2/H 8 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Product data IP/IPH/IPA/IPAH IE & IEA Registers Registers IE0 IE1 Global Individual Disable Enables Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Highest Priority Interrupt Interrupt Polling Sequence Lowest Priority Interrup 002aaa544 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Serial Port Interrupt Priority Low Bit. PT1 Timer 1 Interrupt Priority Low Bit. PX1 External Interrupt 1 Priority Low Bit. PT0 Timer 0 Interrupt Priority Low Bit. PX0 External Interrupt 0 Priority Low Bit. Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core ET1 EX1 ET0 4 ...
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... Description - Reserved for future use. Should be set to ‘0’ by user programs. PBOH Brown-out interrupt priority bit. - Reserved for future use. Should be set to ‘0’ by user programs. Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core PT1H PX1H PT0H ...
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... Be sure to DD voltage long enough at its normal operating level for the oscillator to restart DD Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core , the interrupt service routine program IH © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Table 59 shows the typical values for C1 and C2 vs. Recommended values for C1 and C2 by crystal type Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Exited by Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits idle mode, ...
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... Security bit. - Reserved for future use. Should be set to ‘0’ by user programs. EDC Enable double clock. - Reserved for future use. Should be set to ‘0’ by user programs. Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core NC XTAL2 external oscillator XTAL1 signal ...
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... Product data Conditions amb 10 seconds 3 seconds Operating range Description ambient temperature under bias commercial industrial supply voltage oscillator frequency oscillator frequency for in-application programming Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Min Max 55 +125 65 +150 0 0 1.0 DD ...
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... I/O pin capacitance [1] input capacitance pin inductance This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Units Test method cycles JEDEC Standard A117 years ...
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... C to +70 C amb +85 C amb must be externally limited as follows: OL may exceed the related specification. Pins are not guaranteed to sink current greater than the OH Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core = 0 V Min 0.5 0.2V + 0 ...
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... ALE and PSEN to momentarily fall below the V OH Maximum Active I DD Typical Active Internal Clock Frequency (MHz) Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core s of ALE and Ports 1 and 3. The noise OL 0.7 specification when DD Maximum Idle I DD Typical Idle 002aaa547 © ...
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... Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core = 0 V Variable Min Max CLCL CLCL CLCL - 4T 65 CLCL CLCL CLCL - 3T 55 ...
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... Time from Address Valid to ALE LOW AVLL = Time from ALE LOW to PSEN LOW LLPL t LHLL t LLPL t PLAZ t LLAX AVIV A8 - A15 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core t PLPH t LLIV t PLIV t PXAV t PXIZ t PXIX INSTR A15 002aaa548 © ...
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... QVWH DATA OUT t AVWL P2[7:0] or A8-A15 FROM DPH Oscillator 12 MHz Min Max - - Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core t WHLH t WHQX A0-A7 FROM PCL INSTR IN A8-A15 FROM PCH 002aaa549 t WHLH t WHQX A0-A7 FROM PCL INSTR IN A8-A15 FROM PCH 002aaa550 Variable Min ...
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... XLXL t XHQX t QVXH XHDX t XHDV VALID VALID VALID VALID Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Variable Min Max 0.35T 0.65T CLCL CLCL - - - - t CHCX t CLCH 002aaa551 Variable Min Max 12t - CLCL 10t ...
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... V LOAD - 0.1V /V level occurs mA tester to DUT Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core LOW Test V IHT -V INPUT HIGH Test V ILT - V INPUT LOW Test 002aaa553 (0.45 V) for a logic 0. Measurement reference ILT 0. 0. 0.1V 002aaa554 C L 002aaa555 © ...
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... XTAL2 CLOCK XTAL1 SIGNAL RST EA (NC) XTAL2 XTAL1 V SS 002aaa558 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core V DD 002aaa556 V DD 002aaa557 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... 1.70 0.53 0.36 52.5 14.1 1.14 0.38 0.23 51.5 13.7 0.067 0.021 0.014 2.067 0.56 0.045 0.015 0.009 2.028 0.54 REFERENCES JEDEC JEITA MO-015 SC-511-40 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core 3.60 15.80 17.42 2.54 15.24 3.05 15.24 15.90 0.14 0.62 0.69 0.1 0.6 0.12 0.60 0.63 EUROPEAN PROJECTION © ...
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... 0.45 0.18 10.1 10.1 12.15 12.15 0.8 0.30 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC JEITA MS-026 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core detail 0.75 1.2 1 0.2 0.2 0.1 0.45 0.8 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... 0.81 16.66 16.66 16.00 16.00 17.65 1.27 0.66 16.51 16.51 14.99 14.99 17.40 0.032 0.656 0.656 0.63 0.63 0.695 0.05 0.026 0.650 0.650 0.59 0.59 0.685 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core detail 17.65 1.22 1.44 0.18 0.18 0.1 17.40 1.07 1.02 0.695 ...
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... Product data (9397 750 11669); ECN 853-2432 30075 dated 27 June 2003 9397 750 14101 Product data Updated Flash memory information Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core (Section 7.1). © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Rev. 03 — 11 October 2004 P89LV51RD2 8-bit microcontrollers with 80C51 core Fax: + 24825 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 11 October 2004 Document order number: 9397 750 14101 P89LV51RD2 8-bit microcontrollers with 80C51 core 7.6.2 SPI description . . . . . . . . . . . . . . . . . . . . . . . . 42 7.7 Watchdog timer ...