PIC16LF628A-I/SO Microchip Technology, PIC16LF628A-I/SO Datasheet - Page 88

• Manufacturer Part Number: PIC16LF628A-I/SO
• Description: IC MCU FLASH 2KX14 EEPROM 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF628A-I/SO

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16LF
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Package: 18SOIC W
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Interface Type: USART
• Number Of Timers: 3
• Processor Series: PIC16LF
• Core: PIC
• Data Ram Size: 224 B
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PIC16F627A/628A/648A
12.4.2
Once Synchronous mode is selected, reception is
enabled
(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is
sampled on the RB1/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set, then CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt flag bit
RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register (i.e., it is a two-
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The 9th
receive bit is buffered the same way as the receive
data. Reading the RCREG register, will load bit RX9D
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
DS40044G-page 88
Legend:
Address
0Ch
1Ah
8Ch
18h
98h
99h
by
RCREG USART Receive Data Register
SPBRG Baud Rate Generator Register
RCSTA
TXSTA
USART SYNCHRONOUS MASTER
RECEPTION
Name
PIR1
PIE1
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous master reception.
setting
CSRC
SPEN
EEIF
EPIE
Bit 7
either
CMIE
CMIF
Bit 6
RX9
TX9
enable
SREN CREN
TXEN SYNC
RCIF
RCIE
Bit 5
bit
Bit 4
TXIF
TXIE
SREN
ADEN
Bit 3
—
—
—
CCP1IF TMR2IF TMR1IF 0000 -000
CCP1IE TMR2IE TMR1IE -000 0000
BRGH
FERR
Follow these steps when setting up a Synchronous
Master Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Read the 8-bit received data by reading the
11. If an OERR error occurred, clear the error by
Bit 2
TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
Initialize the SPBRG register for the appropriate
baud rate. (Section 12.1 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
RCREG register.
clearing bit CREN.
OERR
TRMT
Bit 1
RX9D
TX9D
Bit 0
© 2009 Microchip Technology Inc.
0000 000x
0000 0000
0000 -010
0000 0000
Value on:
POR
other Resets
Value on all
0000 -000
0000 000x
0000 0000
-000 -000
0000 -010
0000 0000