PIC16F1937-I/P Microchip Technology, PIC16F1937-I/P Datasheet
PIC16F1937-I/P
Specifications of PIC16F1937-I/P
Available stocks
Related parts for PIC16F1937-I/P
PIC16F1937-I/P Summary of contents
Page 1
... LCD Driver and nanoWatt Technology © 2008 Microchip Technology Inc. PIC16F193X/LF193X 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Preliminary Data Sheet DS41364A ...
Page 2
... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... Flash-Based, 8-Bit CMOS Microcontrollers Devices Included In This Data Sheet: PIC16F193X Devices: • PIC16F1933 • PIC16F1934 • PIC16F1936 • PIC16F1937 • PIC16F1938 • PIC16F1939 PIC16LF193X Devices: • PIC16LF1933 • PIC16LF1934 • PIC16LF1936 • PIC16LF1937 • PIC16LF1938 • PIC16LF1939 High-Performance RISC CPU: • ...
Page 4
... PIC16F1933 4096 256 256 PIC16LF1933 PIC16F1934 4096 256 256 PIC16LF1934 PIC16F1936 8192 256 512 PIC16LF1936 PIC16F1937 8192 256 512 PIC16LF1937 PIC16F1938 16384 256 1024 PIC16LF1938 PIC16F1939 16384 256 1024 PIC16LF1939 Note 1: COM3 and SEG15 share the same physical pin on PIC16F1933/1936/1938/PIC16LF1933/1936/1938, therefore, SEG15 is not available when using 1/4 multiplex displays ...
Page 5
... SEG2/CLKIN/OSC1/RA7 CAP (2) SEG1/V /CLKOUT/OSC2/RA6 (1) P2B /T1CKI/T1OSO/RC0 (1) (1) P2A /CCP2 /T1OSI/RC1 SEG3/P1A/CCP1/RC2 SEG6/SCL/SCK/RC3 Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. © 2008 Microchip Technology Inc. PIC16F193X/LF193X PIC16F1933/1936/1938, PIC16LF1933/1936/1938) ( RB7/ICSPDAT/ICDDAT/SEG13 28 1 RB6/ICSPCLK/ICDCLK/SEG14 27 2 RB5/AN13/CPS5/P2B RB4/AN11/CPS4/P1D/COM0 4 RB3/AN9/C12IN2-/CPS3/CCP2 ...
Page 6
... SEG5 /V /SS /SRNQ/CPS7/C2OUT /AN4/RA5 CAP SEG2/CLKIN/OSC1/RA7 (2) SEG1/V /CLKOUT/OSC2/RA6 CAP Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. DS41364A-page PIC16F1933/1936/1938 4 18 PIC16LF1933/1936/1938 RC7/RX/DT/P3B/SEG8 15 Preliminary (1) (1) RB3/AN9/C12IN2-/CPS3/CCP2 /P2A /VLCD3 RB2/AN8/CPS2/P1B/VLCD2 RB1/AN10/C12IN3-/CPS1/P1C/VLCD1 RB0/AN12/CPS0/CCP4/SRI/INT/SEG0 DD SS © 2008 Microchip Technology Inc. ...
Page 7
... DD Vss 8, 5, — — — Note 1: Pin functions can be moved using the APFCON register. 2: PIC16F193X devices only. © 2008 Microchip Technology Inc. PIC16F193X/LF193X — — — (1) SRNQ SS — — — — — — — — — — ...
Page 8
... PIC16F193X devices only. DS41364A-page /AN4/RA5 7 34 /AN5/RE0 Preliminary RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCLK/SEG14 (1) (1) (1) RB5/AN13/CPS5/CCP3 /P3A /T1G /COM1 RB4/AN11/CPS4/COM0 (1) (1) RB3/AN9/C12IN2-/CPS3/CCP2 /P2A /VLCD3 RB2/AN8/CPS2/VLCD2 RB1/AN10/C12IN3-/CPS1/VLCD1 RB0/AN12/CPS0/SRI/INT/SEG0 RD7/CPS15/P1D/SEG20 RD6/CPS14/P1C/SEG19 RD5/CPS13/P1B/SEG18 RD4/CPS12/P2D/SEG17 RC7/RX/DT/SEG8 RC6/TX/CK/SEG9 RC5/SDO/SEG10 (1) RC4/SDI/SDA/T1G /SEG11 RD3/CPS11/P2C/SEG16 (1) RD2/CPS10/P2B © 2008 Microchip Technology Inc. ...
Page 9
... Pin Diagram – PIC16F1934/1937/1939, PIC16LF1934/1937/1939) 44-Pin QFN ( 44-pin QFN SEG8/DT/RX/RC7 SEG17/P2D/CPS12/RD4 SEG18/P1B/CPS13/RD5 SEG19/P1C/CPS14/RD6 SEG20/P1D/CPS15/RD7 SEG0/INT/SRI/CPS0/AN12/RB0 VLCD1/CPS1/C12IN3-/AN10/RB1 VLCD2/CPS2/AN8/RB2 Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 1 RA6/OSC2/CLKOUT RA7/OSC1/CLKIN/SEG2 PIC16F1934/1937/1939 PIC16LF1934/1937/1939 DD 7 RE2/AN7/CCP5/SEG23 ...
Page 10
... Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. DS41364A-page RC0/T1OSO/T1CKI/P2B RA6/OSC2/CLKOUT/V 3 RA7/OSC1/CLKIN/SEG2 PIC16F1934/1937/1939 PIC16LF1934/1937/1939 RE2/AN7/CCP5/SEG23 27 7 RE1/AN6/P3B/SEG22 26 8 RE0/AN5/CCP3 9 25 RA5/AN4/C2OUT RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4 Preliminary (1) (2) /SEG1 CAP (1) (1) /P3A /SEG21 (1) (1) (1) (2) /CPS7/SRNQ /SS /V /SEG5 CAP © 2008 Microchip Technology Inc. ...
Page 11
... Vss 12, 6, 6,30, — — — Note 1: Pin functions can be moved using the APFCON register. © 2008 Microchip Technology Inc. PIC16F193X/LF193X — — — (1) SRNQ (1) — — — — — — — — — — — — ...
Page 12
... Packaging Information.............................................................................................................................................................. 391 Appendix A: Revision History............................................................................................................................................................. 403 Appendix B: Device Differences......................................................................................................................................................... 403 Index .................................................................................................................................................................................................. 405 The Microchip Web Site ..................................................................................................................................................................... 413 Customer Change Notification Service .............................................................................................................................................. 413 Customer Support .............................................................................................................................................................................. 413 Reader Response .............................................................................................................................................................................. 414 Product Identification System............................................................................................................................................................. 415 DS41364A-page 10 ) ................................................................................................................................ 335 ™ Preliminary © 2008 Microchip Technology Inc. ...
Page 13
... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Preliminary DS41364A-page 11 ...
Page 14
... PIC16F193X/LF193X NOTES: DS41364A-page 12 Preliminary © 2008 Microchip Technology Inc. ...
Page 15
... Internal Internal Internal Oscillator Oscillator Oscillator Block Block Block Timer0 Timer1 Comparators CCP4/5 ECCP1/2/3 © 2008 Microchip Technology Inc. PIC16F193X/LF193X Data Bus Data Bus Data Bus Program Counter Program Counter Program Counter 16-Level Stack 8 Level Stack 8 Level Stack RAM (13-bit) (15-bit) ...
Page 16
... Addressing, INDF and FSR Registers” for more details. 1.1.3 INSTRUCTION SET There are 48 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 26.0 “Instruction Set Summary” for more details. DS41364A-page 14 “Indirect Preliminary © 2008 Microchip Technology Inc. ...
Page 17
... Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only © 2008 Microchip Technology Inc. PIC16F193X/LF193X Input Output Type Type TTL CMOS General purpose I/O. AN — ...
Page 18
... Comparator negative input. AN — Capacitive sensing input 3. ST CMOS Capture/Compare/PWM2. — CMOS PWM output. AN — LCD analog input. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels © 2008 Microchip Technology Inc. ...
Page 19
... Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only © 2008 Microchip Technology Inc. PIC16F193X/LF193X Input Output Type Type TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. ...
Page 20
... LCD analog output. ST CMOS General purpose I/O. AN — Capacitive sensing input 13. — CMOS PWM output. — AN LCD analog output. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels © 2008 Microchip Technology Inc. ...
Page 21
... Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only © 2008 Microchip Technology Inc. PIC16F193X/LF193X Input Output Type Type ST CMOS General purpose I/O. AN — Capacitive sensing input 14. ...
Page 22
... PIC16F193X/LF193X NOTES: DS41364A-page 20 Preliminary © 2008 Microchip Technology Inc. ...
Page 23
... The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 2-1, 2-2 and 2-3). TABLE 2-1: DEVICE SIZES AND ADDRESSES Device / PIC16F1933 PIC16LF1933 / PIC16F1934 PIC16LF1934 / PIC16F1936 PIC16LF1936 / PIC16F1937 PIC16LF1937 / PIC16F1938 PIC16LF1938 / PIC16F1939 PIC16LF1939 © 2008 Microchip Technology Inc. PIC16F193X/LF193X Program Memory Space (Words) 4,096 4,096 8,192 8,192 ...
Page 24
... INTERRUPT, RETFIE 0000h 0004h 0005h 07FFh 0800h On-chip 0FFFh Program 1000h Memory 7FFFh Preliminary PROGRAM MEMORY MAP AND STACK FOR THE PIC16F1936/PIC16LF1936/ PIC16F1937/PIC16LF1937 PC<14:0> 15 Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh ...
Page 25
... Page 1 Page 2 Page 3 Page 4 Page 7 Rollover to Page 0 Rollover to Page 7 © 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in pro- gram memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory ...
Page 26
... Registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in the following sections. The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. DS41364A-page 24 Preliminary © 2008 Microchip Technology Inc. ...
Page 27
TABLE 2-2: PIC16F1933/1934 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...
Page 28
TABLE 2-3: PIC16F1933/1934 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h ...
Page 29
TABLE 2-4: PIC16F1936/1937 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...
Page 30
TABLE 2-5: PIC16F1936/1937 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h ...
Page 31
TABLE 2-6: PIC16F1938/1939 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...
Page 32
TABLE 2-7: PIC16F1938/1939 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h ...
Page 33
TABLE 2-8: PIC16F193X/LF193X MEMORY MAP, BANKS 16-23 BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H ...
Page 34
TABLE 2-9: PIC16F193X/LF193X MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...
Page 35
... Unimplemented Read as ‘0’ 7EFh Legend: = Unimplemented data memory locations, read as ‘0’. © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-11: PIC16F1934/1937/1939 MEMORY MAP, BANK 15 Bank 15 LCDCON 791h LCDPS 792h LCDREF 793h LCDCST 794h ...
Page 36
... Read as ‘0’ FE3h STATUS_SHAD FE4h WREG_SHAD FE5h BSR_SHAD FE6h PCLATH_SHAD FE7h FSR0L_SHAD FE8h FSR0H_SHAD FE9h FSR1L_SHAD FEAh FSR1H_SHAD FEBh — FECh FEDh STKPTR FEEh TOSL FEFh TOSH Legend: = Unimplemented data memory locations, read as ‘0’. DS41364A-page 34 Preliminary © 2008 Microchip Technology Inc. ...
Page 37
... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 38
... SCS1 SCS0 0011 1-00 0011 1-00 LFIOFR HFIOFR 00q0 0q0- qqqq qq0- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF1 ADPREF0 0000 -000 0000 -000 — — © 2008 Microchip Technology Inc. ...
Page 39
... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 40
... BRG1 BRG0 0000 0000 0000 0000 BRG9 BRG8 0000 0000 0000 0000 OERR RX9D 0000 000x 0000 000x TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00 © 2008 Microchip Technology Inc. ...
Page 41
... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 42
... STR1B STR1A ---0 0001 ---0 0001 — — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M1 CCP2M0 0000 0000 0000 0000 P2DC1 P2DC0 0000 0000 0000 0000 STR2B STR2A ---0 0001 ---0 0001 C5TSEL1 C5TSEL0 ---- --00 ---- --00 © 2008 Microchip Technology Inc. ...
Page 43
... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 44
... IOCBP1 IOCBP0 0000 0000 0000 0000 IOCBN1 IOCBN0 0000 0000 0000 0000 IOCBF1 IOCBF0 0000 0000 0000 0000 — — — — — — — — — — — — — — — — — — © 2008 Microchip Technology Inc. ...
Page 45
... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 46
... BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u — — © 2008 Microchip Technology Inc. ...
Page 47
... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 48
... COM2 COM2 SEG17 SEG16 xxxx xxxx uuuu uuuu COM2 COM2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM3 COM3 SEG9 SEG8 xxxx xxxx uuuu uuuu COM3 COM3 SEG17 SEG16 xxxx xxxx uuuu uuuu COM3 COM3 — — © 2008 Microchip Technology Inc. ...
Page 49
... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 50
... Microchip Technology Inc. ...
Page 51
... STATUS • FSR0 Low • FSR0 High • FSR1 Low • FSR1 High • BSR • WREG • PCLATH • INTCON Note: The core registers are the first 12 addresses of every data memory bank. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Preliminary DS41364A-page 49 ...
Page 52
... Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. R-1/q R-1 Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition (ADDWF, ADDLW, SUBLW, SUBWF instructions) Preliminary R/W-x/x R/W-x/x R/W-x/x (1) ( bit 0 (1) (1) © 2008 Microchip Technology Inc. ...
Page 53
... PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate 000 001 010 011 100 101 110 111 © 2008 Microchip Technology Inc. PIC16F193X/LF193X R/W-1/1 R/W-1/1 R/W-1/1 T0SE PSA U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets /4) OSC ...
Page 54
... PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). Note 1: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. Preliminary © 2008 Microchip Technology Inc. ...
Page 55
... If the STVREN bit in Configuration Word 2 is programmed, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.5 Indirect Addressing, INDF and FSR Registers The INDFn registers are not physical registers ...
Page 56
... Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS41364A-page 54 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0x7FFF 0xFFFF Preliminary © 2008 Microchip Technology Inc. ...
Page 57
... FIGURE 2-6: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 0000 0x00 0x7F Bank 0 Bank 1 Bank 2 © 2008 Microchip Technology Inc. PIC16F193X/LF193X Indirect Addressing 7 FSRxH Bank Select 0001 0010 1111 Bank 31 Preliminary ...
Page 58
... FSRnH 1 0 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F Preliminary the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP 7 0 FSRnL 0 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF © 2008 Microchip Technology Inc. ...
Page 59
... LFINTOSC 11-bit Ripple Counter Note 1: See Table 3-5 for time-out situations. 2: PWRT and OST counters are reset by POR and BOR. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal between operation ...
Page 60
... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu © 2008 Microchip Technology Inc. ...
Page 61
... If these conditions are not met, the device must be held in Reset until the operating conditions are met. © 2008 Microchip Technology Inc. PIC16F193X/LF193X For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). ...
Page 62
... Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Change INTOSC divider (IRCF bits) DS41364A-page 60 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Cleared until the end of OST Preliminary © 2008 Microchip Technology Inc. WDT Time-out WDT Cleared Unaffected ...
Page 63
... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. © 2008 Microchip Technology Inc. PIC16F193X/LF193X R/W-1/1 R/W-0/0 R/W-1/1 WDTPS3 WDTPS2 WDTPS1 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 64
... A Reset is DD falls below V for more DD BOR while the Power-up Timer is DD Device Device Operation upon wake- up from Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately V BOR V BOR V BOR © 2008 Microchip Technology Inc. ...
Page 65
... BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active and armed 0 = The Brown-out Reset circuit is disabled or is warming up © 2008 Microchip Technology Inc. PIC16F193X/LF193X U-0 U-0 U-0 — — ...
Page 66
... MCLR high will begin execution immediately (see Figure 3-6). This is useful for testing purposes or to synchronize more than one PIC16F193X/LF193X device operating in parallel. Table 3-7 shows the Reset conditions for some special registers. DS41364A-page 64 Preliminary © 2008 Microchip Technology Inc. ...
Page 67
... BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) © 2008 Microchip Technology Inc. PIC16F193X/LF193X The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 3-3. ...
Page 68
... Illegal set on POR Brown-out Reset WDT Reset WDT Wake-up from Sleep Interrupt Wake-up from Sleep MCLR Reset during normal operation MCLR Reset during Sleep RESET instruction executed Stack Overflow Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) T OST © 2008 Microchip Technology Inc. ...
Page 69
... TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 3-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2008 Microchip Technology Inc. PIC16F193X/LF193X T PWRT T OST DD T PWRT T OST Preliminary ): CASE 3 DS41364A-page 67 ...
Page 70
... Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — Preliminary STATUS PCON Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu Register Bit 1 Bit 0 on Page — BORRDY 63 POR BOR © 2008 Microchip Technology Inc. ...
Page 71
... FIGURE 4-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 4-2) © 2008 Microchip Technology Inc. PIC16F193X/LF193X • Timer0 Overflow Interrupt • Timer1 Gate Interrupt • Timer1 Overflow Interrupt • Timer2 Match with PR2 Interrupt • Timer4 Match with PR4 Interrupt • ...
Page 72
... CCP5IF CCP5IE OSFIF OSFIE TMR1IF TMR1IE • • • • • • TMR6IF TMR6IE C2IF C2IE C1IF C1IE EEIF EEIE BCLIF BCLIE LCDIF LCDIE DS41364A-page 70 Preliminary © 2008 Microchip Technology Inc. To Interrupt Logic (Figure 4-1) ...
Page 73
... CLKOUT is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 28.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. © 2008 Microchip Technology Inc. PIC16F193X/LF193X that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector ...
Page 74
... Upon exit from the Interrupt Service Routine, these reg- isters are automatically restored. Any modifications to these registers during the ISR will be lost. Depending on the user’s application, other registers may also need to be saved. causes an Preliminary © 2008 Microchip Technology Inc. ...
Page 75
... None of the interrupt-on-change pins have changed state Note 1: TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing TMR0IF bit. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...
Page 76
... Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0 © 2008 Microchip Technology Inc. ...
Page 77
... Disables the LCD module interrupt bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt © 2008 Microchip Technology Inc. PIC16F193X/LF193X Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...
Page 78
... Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 U-0 CCP3IE TMR6IE — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 U-0 TMR4IE — bit 0 © 2008 Microchip Technology Inc. ...
Page 79
... No Timer2 to PR2 match occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software The TMR1 register did not overflow © 2008 Microchip Technology Inc. PIC16F193X/LF193X Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 80
... R/W-0/0 R/W-0/0 R/W-0/0 EEIF BCLIF LCDIF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary should ensure the U-0 R/W-0/0 — CCP2IF bit 0 © 2008 Microchip Technology Inc. ...
Page 81
... Unimplemented: Read as ‘0’ bit 1 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 post-scaled match occurred (must be cleared in software TMR4 to PR4 match occurred bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC16F193X/LF193X R/W-0/0 R/W-0/0 R/W-0/0 CCP3IF TMR6IF — ...
Page 82
... TMR6IE — RCIF TXIF SSPIF CCP1IF C1IF EEIF BCLIF LCDIF CCP4IF CCP3IF TMR6IF — Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 73 PS1 PS0 51 TMR2IE TMR1IE 74 — CCP2IE 75 TMR4IE — 76 TMR2IF TMR1IF 77 — CCP2IF 78 TMR4IF — 79 © 2008 Microchip Technology Inc. ...
Page 83
... After the cap is fully charged, the device is released from Reset. For more information, refer to Section 28.0 “Electrical Specifications”. See Configuration Word 2 register (Register 10-2) for V enable bits. CAP © 2008 Microchip Technology Inc. PIC16F193X/LF193X ). Preliminary DS41364A-page 81 ...
Page 84
... PIC16F193X/LF193X NOTES: DS41364A-page 82 Preliminary © 2008 Microchip Technology Inc. ...
Page 85
... Figure 6-1. FIGURE 6-1: GENERIC I/O PORT OPERATION Read LATx TRISx D Q Write LATx Write PORTx CK Data Register Data Bus Read PORTx To peripherals ANSELx © 2008 Microchip Technology Inc. PIC16F193X/LF193X V DD I/O pin V SS Preliminary DS41364A-page 83 ...
Page 86
... The unselected pin will be unaffected. R/W-0/0 R/W-0/0 R/W-0/0 P2BSEL SRNQSEL C2OUTSEL U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets CAP CAP CAP CAP CAP CAP Preliminary R/W-0/0 R/W-0/0 SSSEL CCP2SEL bit 0 © 2008 Microchip Technology Inc. ...
Page 87
... LATA<7:0>: PORTA Output Latch Value bits Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. © 2008 Microchip Technology Inc. PIC16F193X/LF193X TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘ ...
Page 88
... Value at POR and BOR/Value at all other Resets R/W-1/1 R/W-1/1 R/W-1/1 ANSA4 ANSA3 ANSA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. Preliminary R/W-1/1 R/W-1/1 TRISA1 TRISA0 bit 0 R/W-1/1 R/W-1/1 ANSA1 ANSA0 bit 0 © 2008 Microchip Technology Inc. ...
Page 89
... SEG7 (LCD) 2. RA1 RA2 1. COM2 (LCD) 2. DACOUT (DAC) 3. RA2 RA3 1. COM3 (LCD), 28-pin only 2. SEG15 (LCD) 3. RA3 © 2008 Microchip Technology Inc. PIC16F193X/LF193X RA4 1. SEG4 (LCD) 2. SRQ (SR Latch) 3. C1OUT (Comparator) 4. CCP5 (CCP), 28-pin only 5. RA4 RA5 1. V (enabled by Configuration Word) CAP 2 ...
Page 90
... C2SYNC 148 CPSOUT T0XCS 180 CPSCH1 CPSCH0 181 — — 128 --- DACNSS 153 LATA1 LATA0 85 LMUX1 LMUX0 243 SE1 SE0 247 SE9 SE8 247 PS1 PS0 51 RA1 RA0 85 SRPS SRPR 122 SSPM1 SSPM0 277 TRISA1 TRISA0 86 © 2008 Microchip Technology Inc. ...
Page 91
... Note: The ANSELB register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.3.1 WEAK PULL-UPS Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:0> enable or ...
Page 92
... Value at POR and BOR/Value at all other Resets (1) R/W-1/1 R/W-1/1 R/W-1/1 WPUB4 WPUB3 WPUB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u RB1 RB0 bit 0 R/W-x/u R/W-x/u LATB1 LATB0 bit 0 R/W-1/1 R/W-1/1 WPUB1 WPUB0 bit 0 © 2008 Microchip Technology Inc. ...
Page 93
... Digital I/O. Pin is assigned to port or digital special function Analog input. Pin is assigned as analog input Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. © 2008 Microchip Technology Inc. PIC16F193X/LF193X R/W-1/1 R/W-1/1 R/W-1/1 ...
Page 94
... IOCBN1 IOCBN0 104 IOCBF1 IOCBF0 104 LATB2 LATB1 LATB0 90 CS0 LMUX1 LMUX0 243 SE2 SE1 SE0 247 SE10 SE9 SE8 247 PS2 PS1 PS0 51 RB2 RB1 RB0 90 T1GSS1 T1GSS0 170 TRISB2 TRISB1 TRISB0 91 WPUB2 WPUB1 WPUB0 90 © 2008 Microchip Technology Inc. ...
Page 95
... Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. © 2008 Microchip Technology Inc. PIC16F193X/LF193X The TRISC register (Register 6-13) controls the PORTC pin output drivers, even when they are being used as analog inputs ...
Page 96
... PORTC pin configured as an input (tri-stated PORTC pin configured as an output DS41364A-page 94 R/W-1/1 R/W-1/1 R/W-1/1 TRISC4 TRISC3 TRISC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-1/1 R/W-1/1 TRISC1 TRISC0 bit 0 © 2008 Microchip Technology Inc. ...
Page 97
... SMP CKE T1CON TMR1CS1 TMR1CS0 TXSTA CSRC TX9 TRISC TRISC7 TRISC6 Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. © 2008 Microchip Technology Inc. PIC16F193X/LF193X RC5 1. SEG10 (LCD) 2. SDL (MSSP) 3. RC5 RC6 1. SEG9 (LCD (EUSART) 3 ...
Page 98
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1,2) Preliminary INITIALIZING PORTD ; ;Init PORTD ;Make PORTD digital ; ;Set RD<3:2> as inputs ;and set RD<7:4,1:0> ;as outputs R/W-x/u R/W-x/u RD1 RD0 bit 0 R/W-x/u R/W-x/u LATD1 LATD0 bit 0 © 2008 Microchip Technology Inc. ...
Page 99
... ANSELD register is not implemented on the PIC16F1933/1936/1938. Read as ‘0’. 3: PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. © 2008 Microchip Technology Inc. PIC16F193X/LF193X will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. ...
Page 100
... RD5 RD4 RD3 RD2 TRISD5 TRISD4 TRISD3 TRISD2 Preliminary (1) Register on Bit 1 Bit 0 Page ANSD1 ANSD0 97 CCPxM1 CCPxM0 184 CPSOUT T0XCS 180 CPSCH1 CPSCH0 181 LATD1 LATD0 96 LMUX1 LMUX0 243 SE17 SE16 247 RD1 RD0 96 TRISD1 TRISD0 97 © 2008 Microchip Technology Inc. ...
Page 101
... Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of actual I/O pin values. © 2008 Microchip Technology Inc. PIC16F193X/LF193X port pins are read, this value is modified and then written to the PORT data latch. RE3 reads ‘0’ when MCLRE = 1. Note 1: RE< ...
Page 102
... The weak pull-up device is automatically disabled if the pin is in configured as an output. DS41364A-page 100 U-0 R/W-1/1 U-0 WPUE3 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary © 2008 Microchip Technology Inc. U-0 U-0 — — bit 0 ...
Page 103
... When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2: ANSELE register is not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938. Read as ‘0’ © 2008 Microchip Technology Inc. PIC16F193X/LF193X The TRISE register (Register 6-21) controls the PORTE pin output drivers, even when they are being used as analog inputs ...
Page 104
... TRISE2 — — WPUE3 — Preliminary (1) Register Bit 1 Bit 0 on Page 137 GO/DONE ADON ANSE1 ANSE0 101 CCPxM1 CCPxM0 184 LATE1 LATE0 99 LMUX1 LMUX0 243 SE17 SE16 247 RE1 RE0 99 TRISE1 TRISE0 101 — — 100 © 2008 Microchip Technology Inc. ...
Page 105
... IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCBFx bits. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 7.4 Clearing Interrupt Flags The individual status flags, (IOCBFx bits), can be cleared by resetting them to zero ...
Page 106
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 IOCBF4 IOCBF3 IOCBF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 IOCBP1 IOCBP0 bit 0 R/W-0/0 R/W-0/0 IOCBN1 IOCBN0 bit 0 R/W-0/0 R/W-0/0 IOCBF1 IOCBF0 bit 0 © 2008 Microchip Technology Inc. ...
Page 107
... IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB TRISB7 TRISB6 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupt-on-Change. © 2008 Microchip Technology Inc. PIC16F193X/LF193X IOCBFx From all other IOCBFx individual pin detectors Q2 Clock Cycle Bit 5 Bit 4 Bit 3 ...
Page 108
... PIC16F193X/LF193X NOTES: DS41364A-page 106 Preliminary © 2008 Microchip Technology Inc. ...
Page 109
... MHz (HFINTOSC) 31 kHz Source 500 kHz 500 kHz Source (MFINTOSC) 31 kHz (LFINTOSC) © 2008 Microchip Technology Inc. PIC16F193X/LF193X The oscillator module can be configured in one of six clock modes – External clock – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode ...
Page 110
... Reset state depends on state of the IESO Configuration bit. 2: Duplicate frequency derived from HFINTOSC. DS41364A-page 108 R/W-1/1 R/W-1/1 U-0 IRCF1 IRCF0 — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 SCS1 SCS0 bit 0 © 2008 Microchip Technology Inc. ...
Page 111
... Upon restarting the external clock, the device will resume operation time had elapsed. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.4 External Clock Modes 8 ...
Page 112
... DD ® ® and PIC ® Oscillator Design” ® Oscillator CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic P (3) R (2) R Sleep F OSC2/CLKOUT ( may be required for S varies with the Oscillator mode © 2008 Microchip Technology Inc. ...
Page 113
... The user also needs to take into account variation due to tolerance of external RC components used. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.5 Internal Clock Modes The oscillator module has three independent, internal oscillators that can be configured or selected as the system clock source ...
Page 114
... LCD • Power-up Timer (PWRT) • Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. Oscillator Preliminary © 2008 Microchip Technology Inc. ...
Page 115
... Internal Oscillator (LFINTOSC) is ready and can be switched kHz Internal Oscillator (LFINTOSC) is not ready bit 0 HFIOFS: High Frequency Internal Oscillator Stable bit (0.5% Stable MHz Internal Oscillator (HFINTOSC communications stable MHz Internal Oscillator (HFINTOSC) is not yet communications stable © 2008 Microchip Technology Inc. PIC16F193X/LF193X R-0/q R-0/q R-q/q HFIOFR ...
Page 116
... Monitor (FSCM) and peripherals, are not affected by the change in frequency. MFINTOSC R/W-0/0 R/W-0/0 R/W-0/0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TUN1 TUN0 bit 0 © 2008 Microchip Technology Inc. ...
Page 117
... Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.5.8 INTERNAL OSCILLATOR CLOCK SWITCH TIMING ...
Page 118
... System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock DS41364A-page 116 Start-up Time 2-cycle Sync = 0 2-cycle Sync = 0 0 LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync ≠ 0 Preliminary Running Running Running © 2008 Microchip Technology Inc. ...
Page 119
... OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.7 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution ...
Page 120
... CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1), or the internal oscillator Preliminary © 2008 Microchip Technology Inc. ...
Page 121
... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...
Page 122
... LCDIE C1IF EEIF BCLIF LCDIF T1CKPS0 T1OSCEN T1SYNC Preliminary Failure Detected Test Register Bit 1 Bit 0 on Page FOSC1 FOSC0 126 SCS1 SCS0 108 LFIOFR HFIOFS 113 TUN1 TUN0 114 — CCP2IE 75 — CCP2IF 78 — TMR1ON 169 © 2008 Microchip Technology Inc. ...
Page 123
... and simultaneously Pulse generator causes a 1 Q-state pulse width. 3: Name denotes the connection point at the comparator output. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 9.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs. Both of the SR latch outputs may be directly output to an I/O pin at the same time ...
Page 124
... MHz 250 kHz R/S-0/0 R/S-0/0 SRPS SRPR bit 0 © 2008 Microchip Technology Inc. ...
Page 125
... SRRC2E: SR Latch C2 Reset Enable bit Comparator output resets SR Latch Comparator output has no effect on SR Latch bit 0 SRRC1E: SR Latch C1 Reset Enable bit Comparator output resets SR Latch Comparator output has no effect on SR Latch © 2008 Microchip Technology Inc. PIC16F193X/LF193X R/W-0/0 R/W-0/0 R/W-0/0 SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘ ...
Page 126
... PIC16F193X/LF193X NOTES: DS41364A-page 124 Preliminary © 2008 Microchip Technology Inc. ...
Page 127
... Configuration Word 2 registers, Code Protection and Device ID. 10.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 register at 8007h and Configuration Word 2 register at 8008h. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Preliminary DS41364A-page 125 ...
Page 128
... Value at POR and BOR/Value at all other Resets (1) (2) (3) Pin Function Select bit pin function is MCLR; Weak pull-up enabled. pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 (1) Preliminary R/P-1/1 R/P-1/1 CPD CP bit 7 R/P-1/1 R/P-1/1 FOSC1 FOSC0 bit 0 © 2008 Microchip Technology Inc. ...
Page 129
... Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Preliminary DS41364A-page 127 ...
Page 130
... FFFh may be modified by EECON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control 00 = 000h to FFFh write-protected, no addresses may be modified by EECON control 8 kW FLASH memory (PIC16F1936/PIC16LF1936 and PIC16F1937/PIC16LF1937 only Write protection off 10 = 000h to 1FFh write-protected, 200h to 1FFFh may be modified by EECON control ...
Page 131
... Program/Verify mode. Only the Least Significant 7 bits of the ID locations are ® reported when using MPLAB IDE. “PIC16193X/PIC16LF193X Memory Specification” (DS41360A) for more information. © 2008 Microchip Technology Inc. PIC16F193X/LF193X See the Programming Preliminary DS41364A-page 129 ...
Page 132
... PIC16F193X/LF193X NOTES: DS41364A-page 130 Preliminary © 2008 Microchip Technology Inc. ...
Page 133
... Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2: See Section 10.0 “Fixed Voltage Reference” for more information. © 2008 Microchip Technology Inc. PIC16F193X/LF193X The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. ...
Page 134
... Table 11-1 gives examples of appro- priate ADC clock selections. Note: Unless using the F system clock frequency will change the ADC clock adversely affect the ADC result. Preliminary © 2008 Microchip Technology Inc. peri- AD specifica any changes in the RC frequency, which ...
Page 135
... Sleep. FIGURE 11-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit © 2008 Microchip Technology Inc. PIC16F193X/LF193X ) V . DEVICE OPERATING FREQUENCIES AD S Device Frequency (F Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) 200 ns ...
Page 136
... ADCON1 register controls the output format. Figure 11-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 © 2008 Microchip Technology Inc. ...
Page 137
... Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 11.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 138
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ; ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Vdd Vref, AN0, On ;Acquisiton delay ;Start conversion ;Is conversion done? ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space © 2008 Microchip Technology Inc. ...
Page 139
... This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: See Section 10.0 “Fixed Voltage Reference” for more information. © 2008 Microchip Technology Inc. PIC16F193X/LF193X R/W-0/0 R/W-0/0 R/W-0/0 CHS2 CHS1 CHS0 U = Unimplemented bit, read as ‘ ...
Page 140
... Value at POR and BOR/Value at all other Resets SS - REF DD + REF R/W-x/u R/W-x/u R/W-x/u ADRES6 ADRES5 ADRES4 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 ADPREF1 ADPREF0 bit 0 R/W-x/u R/W-x/u ADRES3 ADRES2 bit 0 © 2008 Microchip Technology Inc. ...
Page 141
... W = Writable bit u = bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result © 2008 Microchip Technology Inc. PIC16F193X/LF193X R/W-x/u R/W-x/u R/W-x/u — — — Unimplemented bit, read as ‘0’ ...
Page 142
... HOLD Preliminary 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED © 2008 Microchip Technology Inc. ...
Page 143
... Threshold Voltage T Note 1: Refer to Section 28.0 “Electrical Specifications” FIGURE 11-5: ADC TRANSFER FUNCTION FFh FEh FDh FCh FBh 04h 03h 02h 01h 00h V SS © 2008 Microchip Technology Inc. PIC16F193X/LF193X V DD Sampling Switch ≈ 0. ≤ Rss R IC LEAKAGE (1) I ≈ 0. ...
Page 144
... ADPREF1 ADPREF0 138 138 139 ANSA1 ANSA0 86 ANSB1 ANSB0 91 ANSE1 ANSE0 101 CCP1M1 CCP1M0 184 INTF RBIF 73 TMR2IE TMR1IE 74 TMR2IF TMR1IF 77 TRISA1 TRISA0 86 TRISB1 TRISB0 91 TRISE1 TRISE0 101 ADFVR1 ADFVR0 156 --- DACNSS 153 DACR1 DACR0 153 © 2008 Microchip Technology Inc. ...
Page 145
... V -, the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 12-1: SINGLE COMPARATOR – V ...
Page 146
... Output of comparator can be frozen during debugging. DS41364A-page 144 (1) Interrupt Interrupt C POL CxHYS D (from Timer1) T1CLK Preliminary CxINTP det Set CxIF CxINTN det C OUT X To Data Bus Q MC OUT X To ECCP PWM Logic C SYNC TRIS bit C OUT Timer1 SYNCC OUT X © 2008 Microchip Technology Inc. ...
Page 147
... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 12.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register ...
Page 148
... Note: To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. Preliminary “Analog-to-Digital Converter DAC © 2008 Microchip Technology Inc. ...
Page 149
... Analog Voltage Threshold Voltage T Note 1: See Section 28.0 “Electrical Specifications” © 2008 Microchip Technology Inc. PIC16F193X/LF193X 12.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 12-3. Since the analog input pins share their connection with a digital input, they have reverse ...
Page 150
... Comparator output to Timer1 and I/O pin is asynchronous. Refer to Figure 12-2. DS41364A-page 148 R/W-0/0 U-0 R/W-1/1 CxPOL CxSP — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 CxHYS CxSYNC bit 0 © 2008 Microchip Technology Inc. ...
Page 151
... Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit © 2008 Microchip Technology Inc. PIC16F193X/LF193X R/W-0/0 U-0 U-0 CxPCH0 — — Unimplemented bit, read as ‘0’ ...
Page 152
... C2SYNC 148 C1NCH1 C1NCH0 149 C2NCH1 C2NCH0 149 MC2OUT MC1OUT 149 ADFVR1 ADFVR0 156 — DACNSS 153 DACR1 DACR0 153 INTF IOCIF 73 — CCP2IF 78 — CCP2IE 75 RC1 RC0 93 LATC1 LATC0 93 TRISC1 TRISC0 94 ANSA1 ANSA0 86 ANSB1 ANSB0 91 © 2008 Microchip Technology Inc. ...
Page 153
... Reading the DACOUT pin when it has been configured for reference voltage output will always return a ‘0’. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to DACOUT ...
Page 154
... PIC16F193X/LF193X FIGURE 13-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM FVR_BUFFER2 REF DACPSS<1:0> 2 DACEN DACNSS<1:0> REF DS41364A-page 152 Digital-to-Analog Converter (DAC Steps Preliminary DACR<4:0> DAC (To Comparator and ADC Modules) CV REF DACOE © 2008 Microchip Technology Inc. ...
Page 155
... DACR<4:0>: DAC Voltage Output Select bits OUT SOURCE Note 1: The output select bits are always right justified to ensure that any number of bits can be used without affecting the register layout. © 2008 Microchip Technology Inc. PIC16F193X/LF193X U-0 R/W-0/0 R/W-0/0 --- DACPSS1 DACPSS0 U = Unimplemented bit, read as ‘0’ ...
Page 156
... Shaded cells are not used with the DAC. DS41364A-page 154 Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR1 CDAFVR0 DACOE --- DACPSS1 DACPSS0 --- DACR4 DACR3 DACR2 Preliminary Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 156 --- DACNSS 153 DACR1 DACR0 153 © 2008 Microchip Technology Inc. ...
Page 157
... R Module Voltage Reference Output Impedance © 2008 Microchip Technology Inc. PIC16F193X/LF193X The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Refer- , with 1.024V, ence Section 11.0 “Analog-to-Digital Converter (ADC) Module” ...
Page 158
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition ( Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR1 CDAFVR0 Preliminary R/W-0/0 R/W-0/0 ADFVR1 ADFVR0 bit 0 (2) (2) (2) (2) Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 156 © 2008 Microchip Technology Inc. ...
Page 159
... From CPSCLK 1 TMR0CS TMR0SE T0XCS © 2008 Microchip Technology Inc. PIC16F193X/LF193X When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written ...
Page 160
... Section 28.0 “Electrical Specifications”. 15.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41364A-page 158 Preliminary © 2008 Microchip Technology Inc. ...
Page 161
... Timer0 Module Register TRISA TRISA7 TRISA6 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. * Page provides register information. © 2008 Microchip Technology Inc. PIC16F193X/LF193X R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 162
... PIC16F193X/LF193X NOTES: DS41364A-page 160 Preliminary © 2008 Microchip Technology Inc. ...
Page 163
... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2008 Microchip Technology Inc. PIC16F193X/LF193X • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • Gate Event Interrupt Figure 16 block diagram of the Timer1 module ...
Page 164
... T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. T1OSCEN System Clock ( OSC Instruction Clock (F x OSC Capacitive Sensing Oscillator x External Clocking on T1CKI Pin 0 Osc.Circuit On T1OSI/T1OSO Pins 1 Preliminary system clock or they can run Clock Source /4) © 2008 Microchip Technology Inc. ...
Page 165
... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 16.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry ...
Page 166
... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Preliminary © 2008 Microchip Technology Inc. ...
Page 167
... T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 16.9 ECCP/CCP Capture/Compare Time Base The CCP modules uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...
Page 168
... PIC16F193X/LF193X FIGURE 16-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 16-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 DS41364A-page 166 Preliminary © 2008 Microchip Technology Inc ...
Page 169
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF © 2008 Microchip Technology Inc. PIC16F193X/LF193X Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41364A-page 167 ...
Page 170
... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF DS41364A-page 168 Set by hardware on falling edge of T1GVAL Preliminary © 2008 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...
Page 171
... This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop © 2008 Microchip Technology Inc. PIC16F193X/LF193X R/W-0/u R/W-0/u R/W-0/u T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ...
Page 172
... Comparator 1 optionally synchronized output (SYNCC1OUT Comparator 2 optionally synchronized output (SYNCC2OUT) DS41364A-page 170 R/W-0/u R/W-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/u R/W-0/u T1GSS1 T1GSS0 bit 0 © 2008 Microchip Technology Inc. ...
Page 173
... TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T1CON TMR1GE T1GPOL T1GCON Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ...
Page 174
... PIC16F193X/LF193X NOTES: DS41364A-page 172 Preliminary © 2008 Microchip Technology Inc. ...
Page 175
... Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure 17-1 for a block diagram of Timer2/4/6. FIGURE 17-1: TIMER2/4/6 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 TxCKPS<1:0> © 2008 Microchip Technology Inc. PIC16F193X/LF193X TMRx Output Reset TMRx Postscaler Comparator 1 PRx TxOUTPS< ...
Page 176
... Timer2/4/6 Operation During Sleep The Timerx timers cannot be operated while the processor is in Sleep mode. The contents of the TMRx the output and PRx registers will remain unchanged while the processor is in Sleep mode. the 4-bit Preliminary © 2008 Microchip Technology Inc. ...
Page 177
... TMRxON: Timerx On bit 1 = Timerx Timerx is off bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler Prescaler is 64 © 2008 Microchip Technology Inc. PIC16F193X/LF193X R/W-0/u R/W-0/u R/W-0/u TOUTPS1 TOUTPS0 TMRxON U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 178
... CCP1IE RCIF TXIF SSPIF CCP1IF CCP4IE CCP3IE TMR6IE CCP4IF CCP3IF TMR6IF Preliminary Register Bit 1 Bit 0 on Page CCP1M0 184 CCP2M0 184 INTF RBIF 73 TMR2IE TMR1IE 74 TMR2IF TMR1IF 77 — TMR4IE — 76 — TMR4IF — 79 173* 173* 175 © 2008 Microchip Technology Inc. ...
Page 179
... CPS12 (1) CPS13 (1) CPS14 (1) CPS15 (1) CPS16 Note 1: Reference Register 18-2 for channels implemented on each device 2: CPSCH3 is not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 CPSON = 0, disabling capacitive sensing, no channel is selected. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Timer0 Module TMR0CS T0XCS F /4 OSC 0 T0CKI Timer1 Module T1CS<1:0> F OSC ...
Page 180
... Refer to Section 16.12 “Timer1 Gate Control Regis- ter” for additional information. TABLE 18-1: TIMER1 ENABLE FUNCTION TMR1ON TMR1GE Preliminary © 2008 Microchip Technology Inc. Timer1 Operation Off Off On Count Enabled by input ...
Page 181
... This frequency should be less than the value obtained during the nominal frequency measurement. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 18.5.3 FREQUENCY THRESHOLD The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator ...
Page 182
... Timer0 clock source is controlled by the core/Timer0 module and is F DS41364A-page 180 U-0 R/W-0/0 R/W-0/0 — CPSRNG1 CPSRNG0 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets OSC Preliminary © 2008 Microchip Technology Inc. R-0/0 R/W-0/0 CPSOUT T0XCS bit 0 /4 ...
Page 183
... TRISA6 TRISB TRISB7 TRISB6 TRISD TRISD7 TRISD6 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the capacitive sensing module. © 2008 Microchip Technology Inc. PIC16F193X/LF193X (1, 2) (1) R/W-0/0 R/W-0/0 CPSCH4 CPSCH3 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 184
... PIC16F193X/LF193X NOTES: DS41364A-page 182 Preliminary © 2008 Microchip Technology Inc. ...
Page 185
... Capture/Compare/PWM (ECCP1, ECCP2, ECCP3) and two standard Capture/Compare/PWM module (CCP4 and CCP5). The CCP4 and CCP5 modules are identical in operation. The ECCP1, ECCP2 and ECCP3 modules may also be referred to as CCP1, CCP2, CCP3, as required. © 2008 Microchip Technology Inc. PIC16F193X/LF193X Enhanced Preliminary DS41364A-page 183 ...
Page 186
... CCP Mode Capture Compare PWM R/W-0/0 R/W-0/0 R/W-0/0 DCxB0 CCPxM3 CCPxM2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Reset (1) (1) Preliminary Timer Resource Timer1 Timer1 Timer2 R/W-0/0 R/W-0/0 CCPxM1 CCPxM0 bit 0 © 2008 Microchip Technology Inc. ...
Page 187
... CCP1 is based off Timer 2 in PWM Mode 01 = CCP1 is based off Timer 4 in PWM Mode 10 = CCP1 is based off Timer 6 in PWM Mode 11 = Reserved © 2008 Microchip Technology Inc. PIC16F193X/LF193X timers with auto-reload (Timer2, Timer4 and Timer6), PWM mode on the CCP modules can use any of these timers ...
Page 188
... CCP5 is based off Timer 4 in PWM Mode 10 = CCP5 is based off Timer 6 in PWM Mode 11 = Reserved DS41364A-page 186 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary © 2008 Microchip Technology Inc. R/W-0/0 R/W-0/0 C5TSEL1 C5TSEL0 bit 0 ...
Page 189
... Enable Edge Detect TMR1H CCPxCON<3:0> System Clock (F ) OSC © 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.3.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. ...
Page 190
... INTF IOCIF 73 TMR2IE TMR1IE 74 — CCP2IE 75 TMR4IE — 76 TMR2IF TMR1IF 77 — CCP2IF 78 TMR4IF — 79 — TMR1ON 169 T1GSS1 T1GSS0 170 165 165 TRISA1 TRISA0 86 TRISB1 TRISB0 91 TRISC1 TRISC0 94 TRISD1 TRISD0 97 (2) (2) (2) TRISE1 TRISE0 101 © 2008 Microchip Technology Inc. ...
Page 191
... Note: Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.4.2 TIMER1 MODE SELECTION In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode ...
Page 192
... INTF IOCIF 73 TMR2IE TMR1IE 74 — CCP2IE 75 TMR4IE — 76 TMR2IF TMR1IF 77 — CCP2IF 78 TMR4IF — 79 — TMR1ON 169 T1GSS1 T1GSS0 170 165 165 TRISA1 TRISA0 86 TRISB1 TRISB0 91 TRISC1 TRISC0 94 TRISD1 TRISD0 97 (2) (2) (2) TRISE1 TRISE0 101 © 2008 Microchip Technology Inc. ...
Page 193
... Figure 19-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 19.5.7 “Setup for PWM Operation”. © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 19-3: SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle Registers ...
Page 194
... When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure 19-3). Preliminary PULSE WIDTH • CCPRxL:CCPxCON<5:4> • T (TMRx Prescale Value) OSC DUTY CYCLE RATIO ( ) CCPRxL:CCPxCON<5:4> = ---------------------------------------------------------------------- - ( ) 4 PRx + bits of the OSC © 2008 Microchip Technology Inc. ...
Page 195
... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F PWM Frequency 1.22 kHz Timer Prescale (1, 4, 16) 16 PRx Value 0x65 Maximum Resolution (bits) 8 © 2008 Microchip Technology Inc. PIC16F193X/LF193X EQUATION 19-4: PWM RESOLUTION Resolution = Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged ...
Page 196
... TRIS bit(s). Note: In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. Preliminary © 2008 Microchip Technology Inc. ...
Page 197
... Full-Bridge, Reverse 11 Note 1: Pulse Steering enables outputs in Single mode. © 2008 Microchip Technology Inc. PIC16F193X/LF193X The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately ...
Page 198
... Pulse Width = T * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) OSC • Delay = (PWMxCON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWMxCON register (Section 19.6.6 “Programmable Dead-Band Delay Mode”). DS41364A-page 196 Pulse 0 Width Period (1) (1) Delay Delay Preliminary © 2008 Microchip Technology Inc. PRX+1 ...
Page 199
... OSC • Pulse Width = T * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) OSC • Delay = (PWMxCON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWMxCON register (Section 19.6.6 “Programmable Dead-Band Delay Mode”). © 2008 Microchip Technology Inc. PIC16F193X/LF193X Pulse 0 Width Period (1) (1) Delay Delay ...
Page 200
... Note 1: At this time, the TMRx register is equal to the PRx register. 2: Output signals are shown as active-high. FET Driver P1A Load FET Driver P1B V+ FET Driver Load FET Driver Preliminary EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2008 Microchip Technology Inc. ...