PIC18F25J11-I/ML Microchip Technology, PIC18F25J11-I/ML Datasheet - Page 48

• Manufacturer Part Number: PIC18F25J11-I/ML
• Description: IC PIC MCU FLASH 32K 2V 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F25J11-I/ML

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F46J11 FAMILY
3.4.3
In RC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the internal
oscillator block. This mode allows for controllable
power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTOSC block, the primary
oscillator is shut down and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the internal oscillator block. After a
delay of T
begins executing code being clocked by the INTRC.
The IDLEN and SCS bits are not affected by the
wake-up. The INTRC source will continue to run if
either the WDT or the FSCM is enabled.
3.5
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see Section 3.2 “Run Modes”,
Section 3.3 “Sleep Mode” and Section 3.4 “Idle
Modes”).
3.5.1
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 8.0 “Interrupts”).
A fixed delay of interval, T
event, is required when leaving Sleep and Idle modes.
This delay is required for the CPU to prepare for
execution. Instruction execution resumes on the first
clock cycle following this delay.
3.5.2
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
DS39932C-page 48
Exiting Idle and Sleep Modes
CSD
RC_IDLE MODE
EXIT BY INTERRUPT
EXIT BY WDT TIME-OUT
following the wake event, the CPU
CSD
, following the wake
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 25.2 “Watchdog
Timer (WDT)”).
The WDT and postscaler are cleared by one of the
following events:
• Executing a SLEEP or CLRWDT instruction
• The loss of a currently selected clock source (if
3.5.3
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
3.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode (where the primary clock source
• PRI_IDLE mode and the primary clock source is
In these instances, the primary clock source either does
not require an oscillator start-up delay, since it is already
running (PRI_IDLE), or normally does not require an
oscillator start-up delay (EC). However, a fixed delay of
interval, T
when leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes on
the first clock cycle following this delay.
3.6
Deep Sleep mode brings the device into its lowest
power consumption state without requiring the use of
external switches to remove power from the device.
During deep sleep, the on-chip V
regulator is powered down, effectively disconnecting
power to the core logic of the microcontroller.
the FSCM is enabled)
is not stopped) and the primary clock source is
the EC mode
the ECPLL mode
Note:
Deep Sleep Mode
CSD
EXIT BY RESET
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Since Deep Sleep mode powers down the
microcontroller by turning off the on-chip
V
capability is available only on PIC18FXXJ
members in the device family. The on-chip
voltage regulator is not available in
PIC18LFXXJ members of the device
family, and therefore, they do not support
Deep Sleep.
, following the wake event, is still required
DDCORE
mode
voltage regulator, Deep Sleep
© 2009 Microchip Technology Inc.
(see
Section 3.2
DDCORE
voltage
“Run