DSPIC33FJ12MC202-I/SO Microchip Technology, DSPIC33FJ12MC202-I/SO Datasheet - Page 151

• Manufacturer Part Number: DSPIC33FJ12MC202-I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC202-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 12KB (12K x 8)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330021, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164339 - MODULE SKT FOR PM3 28SOICDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.7.2
When the Immediate Update Enable bit is set (IUE =
1), any write to the Duty Cycle registers updates the
new duty cycle value immediately. This feature gives
programmers the option to allow immediate updates of
the active PWM Duty Cycle registers instead of waiting
for the end of the current time base period. Duty cycle
update effects are as follows:
• If the PWM output is active at the time the new
• If the PWM output is active at the time the new
• If the PWM output is inactive at the time the new
System stability is improved in closed-loop servo
applications by reducing the delay between system
observation and the issuance of system corrective
commands when immediate updates are enabled
(IUE = 1).
14.8
In the Complementary mode of operation, each pair of
PWM outputs is obtained by a complementary PWM
signal. A dead time can be inserted during device
switching, when both outputs are inactive for a short
period
Generators”).
In Complementary mode, the duty cycle comparison
units are assigned to the PWM outputs as follows:
• PxDC1 register controls PWM1H/PWM1L outputs
• PxDC2 register controls PWM2H/PWM2L outputs
• PxDC3 register controls PWM3H/PWM3L outputs
© 2007 Microchip Technology Inc.
duty cycle is written and the new duty cycle is less
than the current time base value, the PWM pulse
width will be shortened.
duty cycle is written and the new duty cycle is
greater than the current time base value, the
PWM pulse width will be lengthened.
duty cycle is written and the new duty cycle is
greater than the current time base value, the
PWM output will become active immediately and
will remain active for the new written duty cycle
value.
Complementary PWM Operation
(refer
DUTY CYCLE IMMEDIATE UPDATES
to
Section 14.9
“Dead-Time
Preliminary
dsPIC33FJ12MC201/202
Complementary mode is selected for each PWM
pin pair by clearing the appropriate PMODx bit in the
PWMxCON1 SFR. The PWM I/O pins are set to
Complementary mode by default upon a device Reset.
14.9
Dead-time generation can be provided when any of
the
Complementary Output mode. The PWM outputs use
push-pull drive circuits. Power output devices cannot
switch instantaneously, so some amount of time must
be provided between the turn-off event of one PWM
output in a complementary pair and the turn-on event
of the other transistor.
The PWM module allows two different dead times to be
programmed. These two dead times can be used in
one of two methods to increase user flexibility:
• The PWM output signals can be optimized for
• The two dead times can be assigned to individual
14.9.1
Each complementary output pair for the PWM module
has a 6-bit down counter that is used to produce the
dead-time insertion. As shown in Figure 14-5, each
dead-time unit has a rising and falling edge detector
connected to the duty cycle comparison output.
different turn-off times in the high side and low
side transistors in a complementary pair of tran-
sistors. The first dead time is inserted between
the turn-off event of the lower transistor of the
complementary pair and the turn-on event of the
upper transistor. The second dead time is inserted
between the turn-off event of the upper transistor
and the turn-on event of the lower transistor.
PWM I/O pin pairs. This operating mode allows
the PWM module to drive different transistor/load
combinations with each complementary PWM I/O
pin pair.
PWM
Dead-Time Generators
DEAD-TIME GENERATORS
I/O
pin
pairs
are
DS70265B-page 149
operating
I/O
in