DSPIC33FJ12MC202-I/SO Microchip Technology, DSPIC33FJ12MC202-I/SO Datasheet - Page 185

• Manufacturer Part Number: DSPIC33FJ12MC202-I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC202-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 12KB (12K x 8)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330021, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164339 - MODULE SKT FOR PM3 28SOICDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.5
The 10-bit I2CxADD register contains the Slave mode
addresses.
If the A10M bit (I2CxCON<10>) is ‘0’, the address is
interpreted by the module as a 7-bit address. When an
address is received, it is compared to the 7 Least
Significant bits of the I2CxADD register.
If the A10M bit is ‘1’, the address is assumed to be a
10-bit address. When an address is received, it is
compared with the binary value, ‘11110
(where A9 and A8 are two Most Significant bits of
I2CxADD). If that value matches, the next address will
be compared with the Least Significant 8 bits of
I2CxADD, as specified in the 10-bit addressing
protocol.
TABLE 17-1:
17.6
The I2CxMSK register (Register 17-3) designates
address bit positions as “don’t care” for both 7-bit and
10-bit Address modes. Setting a particular bit location
(= 1) in the I2CxMSK register causes the slave module
to respond, whether the corresponding address bit
value is a ‘0’ or ‘1’. For example, when I2CxMSK is set
to ‘00100000’, the Slave module will detect both
addresses, ‘0000000’ and ‘00100000’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
17.7
The control bit IPMIEN enables the module to support
the Intelligent Peripheral Management Interface (IPMI).
When this bit is set, the module accepts and acts upon
all addresses.
© 2007 Microchip Technology Inc.
0x00
0x01-0x03
0x04-0x07
0x08-0x77
0x78-0x7b
0x7c-0x7f
I
Slave Address Masking
IPMI Support
2
C Module Addresses
7-BIT I
ADDRESSES SUPPORTED BY
dsPIC33FJ12MC201/202
General call address or Start byte
Reserved
Hs mode Master codes
Valid 7-bit addresses
Valid 10-bit addresses
(lower 7 bits)
Reserved
2
C™ SLAVE
A9
Preliminary
A8’
dsPIC33FJ12MC201/202
17.8
The general call address can address all devices.
When this address is used, all devices should, in
theory, respond with an Acknowledgement.
The general call address is one of eight addresses
reserved for specific purposes by the I
consists of all ‘0’s with R_W = 0.
The general call address is recognized when the
General
(I2CxCON<7> = 1). When the interrupt is serviced, the
source for the interrupt can be checked by reading the
contents of the I2CxRCV to determine if the address
was device-specific or a general call address.
17.9
In Slave modes, the module can synchronize buffer
reads and write to the master device by clock stretching.
17.9.1
Both 10-bit and 7-bit Transmit modes implement clock
stretching by asserting the SCLREL bit after the falling
edge of the ninth clock, if the TBF bit is cleared,
indicating the buffer is empty.
In Slave Transmit modes, clock stretching is always
performed, irrespective of the STREN bit. The user’s
ISR must set the SCLREL bit before transmission is
allowed to continue. By holding the SCLx line low, the
user application has time to service the ISR and load
the contents of the I2CxTRN before the master device
can initiate another transmit sequence.
17.9.2
The STREN bit in the I2CxCON register can be used to
enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCLx pin will be held low at
the end of each data receive sequence.
The user’s ISR must set the SCLREL bit before
reception is allowed to continue. By holding the SCLx
line low, the user application has time to service the
ISR and read the contents of the I2CxRCV before the
master device can initiate another receive sequence.
This prevents buffer overruns.
17.10 Software Controlled Clock
When the STREN bit is ‘1’, the software can clear the
SCLREL bit to allow software to control the clock
stretching.
If the STREN bit is ‘0’, a software write to the SCLREL
bit is disregarded and has no effect on the SCLREL bit.
General Call Address Support
Automatic Clock Stretch
Stretching (STREN = 1)
Call
TRANSMIT CLOCK STRETCHING
RECEIVE CLOCK STRETCHING
Enable
(GCEN)
DS70265B-page 183
2
bit
C protocol. It
is
set